Digital phase-locked loop based on Cordic algorithm
A digital phase-locked loop and algorithm technology, applied in the automatic control of power, electrical components, etc., can solve the problems of signal instability, large phase error between digital sine signal and square wave signal, etc., and achieve the effect of short locking time
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[0031] The present invention will be described in more detail below in conjunction with the drawings and specific embodiments.
[0032] See figure 2 As shown, it is a principle block diagram of a digital phase locked loop provided by the present invention. The main modules of the digital phase-locked loop are implemented by a programmable logic device (FPGA) 1. A frequency measurement module 11, a frequency discriminator 12, a digital filter 13, a Cordic oscillator 14 are set in the FPGA1. 14 M divider 15 is set internally.
[0033] The main function of the frequency measurement module 11 is to measure the frequency of the reference clock input signal. In this embodiment, the frequency measurement module 11 adopts a frequency-division frequency measurement method to perform different frequency-division measurements on signals in different frequency bands, and then input the measurement data to the Cordic oscillator 14 to reduce the frequency lock time of the phase-locked loop. T...
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