Digital phase-locked loop based on Cordic algorithm

A digital phase-locked loop and algorithm technology, applied in the automatic control of power, electrical components, etc., can solve the problems of signal instability, large phase error between digital sine signal and square wave signal, etc., and achieve the effect of short locking time

Inactive Publication Date: 2011-05-04
SUN YAT SEN UNIV
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Problems solved by technology

But this method has two defects: one is that the converted sinusoidal signal cannot enter the feedback loop, and the signal is unstable; the other is that the d

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  • Digital phase-locked loop based on Cordic algorithm
  • Digital phase-locked loop based on Cordic algorithm
  • Digital phase-locked loop based on Cordic algorithm

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[0031] The present invention will be described in more detail below in conjunction with the drawings and specific embodiments.

[0032] See figure 2 As shown, it is a principle block diagram of a digital phase locked loop provided by the present invention. The main modules of the digital phase-locked loop are implemented by a programmable logic device (FPGA) 1. A frequency measurement module 11, a frequency discriminator 12, a digital filter 13, a Cordic oscillator 14 are set in the FPGA1. 14 M divider 15 is set internally.

[0033] The main function of the frequency measurement module 11 is to measure the frequency of the reference clock input signal. In this embodiment, the frequency measurement module 11 adopts a frequency-division frequency measurement method to perform different frequency-division measurements on signals in different frequency bands, and then input the measurement data to the Cordic oscillator 14 to reduce the frequency lock time of the phase-locked loop. T...

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Abstract

The invention discloses a digital phase-locked loop based on a Cordic algorithm, comprising: a controller for implementing a phase-locked loop algorithm for outputting a sinusoidal signal; the controller comprises: a frequency measuring module for performing segmental frequency measurement on a reference clock input signal; a phase and frequency discriminator for comparing the reference clock input signal with a feedback signal; a digital filter for equalizing an output signal of the phase and frequency discriminator; and an oscillator for receiving frequency measurement result from the frequency measuring module, generating an output signal having same frequency as the reference clock input signal, and receiving and adjusting phase of the output signal of the digital filter to be synchronous to the reference clock input signal; and a sine wave shaping module which is located at a feedback loop and used for converting the sinusoidal signal into a square signal. Compared with the priorart, the digital phase-locked loop based on the Cordic algorithm outputs a digital sinusoidal signal synchronous to a reference clock signal, and the digital sinusoidal signal is convenient for use in digital signal processing.

Description

technical field [0001] The invention relates to a digital phase-locked loop, in particular to a digital phase-locked loop outputting sinusoidal signals. Background technique [0002] Phase-locked loop (Phase-locked Loop, PLL) is a frequency and phase synchronization technology realized by the principle of feedback control, and its function is to keep the output clock of the circuit synchronized with its external reference clock. When the reference clock frequency or phase changes, the phase-locked loop can detect this change, and adjust the output frequency through the voltage-controlled oscillator until the two are resynchronized. PLL technology is widely used in communication, navigation, radio and television communication, instrument measurement, digital signal processing and national defense technology. [0003] Phase-locked loops can be divided into analog phase-locked loops and digital phase-locked loops. Relatively speaking, digital phase-locked loops have many advan...

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Application Information

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IPC IPC(8): H03L7/08H03L7/099
Inventor 王自鑫何振辉蔡志岗胡庆荣徐辉
Owner SUN YAT SEN UNIV
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