Method for regulating height of isolation structures in EEPROM

Abstract

The invention discloses a method for regulating the height of isolation structures in an electrically erasable programmable read-only memory (EEPROM), which comprises the following steps of: 1, growing a high-voltage gate oxide layer on each of a high-voltage area and a low-voltage area of the EEPROM; 2, spin-coating photoresist on the surface of a silicon wafer, performing exposure and development to expose a tunnelling window and an isolation structure in the high-voltage area of the EEPROM only, and removing part of silicon dioxide in the exposed area and the photoresist on the surface of the silicon wafer by a wet etching process; 3, depositing a layer of polycrystalline silicon on each of the high-voltage area and the low-voltage area of the EEPROM; 4, removing the polycrystalline silicon and the high-voltage gate oxide layer in the low-voltage area of the EEPROM by a photoetching and etching process; and 5, growing a low-voltage gate oxide layer in the low-voltage area of the EEPROM. By the method, the height of the isolation structure in the high-voltage area is the same as that of the isolation structure in the low-voltage area approximately.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process, in particular to an EEPROM manufacturing process. Background technique [0002] Some semiconductor devices, such as EEPROMs, include devices of different voltages to perform various functions. Logic devices with low operating voltage (such as 5V) are mainly used in peripheral circuits and input and output ports, also known as low-voltage devices. A high-voltage device with a relatively high operating voltage (such as greater than 12V) is used in the memory module to provide high voltage for erasing and writing operations. How to integrate low-voltage devices and high-voltage devices, especially how to adjust the height of the isolation structure between the low-voltage device area and the high-voltage device area is a difficult point in process integration. [0003] For the above-mentioned semiconductor devices, such as EEPROM, generally most areas of high-voltage devi...

AI Technical Summary

Problems solved by technology

The different isolation structure heights of the device in the high-voltage area and the low-voltage area are not good for the entire device. If the isolation structure is too high, it will cause the risk of polycrystalline etching residue; if the isolation structure is too low, it will cause the entire device to leak

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