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Method for manufacturing 6-inch POWERMOS transistor epitaxial layer

A manufacturing method and epitaxial layer technology, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of reducing the effective thickness of the epitaxial layer, decreasing the yield of the device, and poor uniformity, so as to suppress the self-doping phenomenon. , Consistency improvement, the effect of improving electrical performance and yield

Active Publication Date: 2012-12-05
FUJIAN FUSHUN MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Due to the self-doping phenomenon, the transition region is widened, thereby reducing the effective thickness of the epitaxial layer
At the same time, the resistivity in the middle is larger than that at the edge, and the transition zone in the middle is narrower than the transition zone at the edge. As a result, the breakdown voltage BVDSS and the on-resistance RDSON distribution of the entire device are poorly distributed, resulting in Device Yield Decline

Method used

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  • Method for manufacturing 6-inch POWERMOS transistor epitaxial layer
  • Method for manufacturing 6-inch POWERMOS transistor epitaxial layer

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Embodiment Construction

[0026] A kind of manufacturing method of 6 inches POWERMOS tube epitaxial layer is characterized in that: carry out according to the following steps:

[0027] 1) Select a suitable POWERMOS tube substrate 1 and perform certain pre-treatments;

[0028] 2) Perform HCL vapor phase corrosion on the substrate at a certain temperature;

[0029] 3) Perform the first H 2 Variable speed purge;

[0030] 4) Deposit a layer of non-doped intrinsic layer 2 with a thickness of 1-2 microns on the substrate;

[0031] 5) Perform the second H 2 Variable speed purge;

[0032] 6) Forming the second epitaxial layer 3 on the intrinsic layer.

[0033] The equipment used in the present invention is the PE-2061S epitaxial furnace produced in Italy, which is heated by high-frequency induction. The base is high-purity graphite whose surface is cracked and coated with a layer of high-purity SiC.

[0034] Reaction chamber, substrate cleaning and treatment of graphite base: When the reaction chamber is...

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Abstract

The invention relates to a method for manufacturing a 6-inch power metal oxide semiconductor (POWERMOS) transistor epitaxial layer. The method is characterized by comprising the following steps of: 1) selecting a suitable POWERMOS transistor substrate slice and performing a certain preprocessing; 2) performing HCl gas-phase corrosion on the substrate slice at a certain temperature; 3) performing primary H2 speed-variable sweeping; 4) depositing an undoped intrinsic layer with the thickness of 1 to 2 mu m on the substrate slice; 5) performing secondary H2 speed-variable sweeping; and 6) forming a second epitaxial layer on the intrinsic layer. By the method, an autodoping phenomenon is inhibited to the maximum at a high temperature and substrate impurities are effectively prevented from diffusing and doping to the epitaxial layer, so that the resistivity uniformity and the width of a transition area are ensured; therefore, the requirements on both the breakdown voltage (BVDSS) and the on-resistance (RDSON) of the device are met.

Description

technical field [0001] The invention relates to a method for manufacturing the epitaxial layer of a 6-inch POWERMOS tube. Background technique [0002] With the development of electronic devices, devices that can control large currents and high voltages are being widely put into practical use. POWERMOS is a kind of device resulting from this. It is very popular because of its precise control. However, compared with general epitaxy, 6-inch POWERMOS epitaxy has a thicker epitaxial layer, high resistivity, and a relatively large surface area, which is 4 inches. 2.25 times and 1.44 times of 5 inches, so there are special requirements and standards for epitaxial wafers. [0003] The structure of the POWERMOS epitaxial wafer is to grow a layer of high resistivity epitaxial layer (N+ / N) on the N+ substrate, which cannot be realized by the ordinary epitaxial process. If the "silicon transfer (mass-transfer)" process is adopted, the base The silicon on the seat will be transferred ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/20H01L21/02
Inventor 万华勇熊爱华梅海军李豪林立桂林善彪
Owner FUJIAN FUSHUN MICROELECTRONICS