Highly integrated wafer fan-out packaging structure
A high-integration, packaging-structure technology, applied in electrical components, electrical solid-state devices, circuits, etc., can solve problems such as single-chip functions, and achieve the effects of avoiding warpage deformation, improving quality, and reducing internal stress
Active Publication Date: 2011-08-31
NANTONG FUJITSU MICROELECTRONICS
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Problems solved by technology
[0004] The final product packaged and manufactured according to the above method has only a single chip function
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[0028] In the following description, many specific details are explained in order to fully understand the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar popularizations without violating the connotation of the present invention. Therefore, the present invention is not limited by the specific implementation disclosed below.
[0029] Secondly, the present invention is described in detail by using schematic diagrams. When describing the embodiments of the present invention in detail, the schematic diagrams are merely examples, which should not limit the scope of protection of the present invention.
[0030] The prior art packaging structure only has a single chip function. If you want to achieve a complete system function, you need to add peripheral circuits including various capacitors, inductors, or resistors in addition to the final product.
[0031] In order t...
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The invention relates to a highly integrated wafer fan-out packaging structure, comprising a to-be-packaged unit, chips and a passive device, wherein the to-be-packaged unit has a function surface; a material-sealing layer is formed on a surface opposite to the function surface of the to-be-packaged unit; the material-sealing layer carries out packaging curing over the to-be-packaged unit; and a groove is arranged between the to-be-packaged units corresponding to the material-sealing layer surface. Compared with the prior art, the highly integrated wafer fan-out packaging structure of the invention firstly integrates chips and passive devices and then carries out packaging, and is a final packaged product having overall system function, instead of single chip function. Furthermore, in thestructure, the entire packaging of the material-sealing layer is decomposed into a plurality of to-be-packaged units, and the internal stress of the material-sealing layer is reduced via the groove between the to-be-packaged units, thereby avoiding warpage of material-sealing layer in the subsequent process of wafer packaging and improving the quality of finished wafer packaging product.
Description
Technical field [0001] The invention relates to semiconductor technology, in particular to a highly integrated wafer fan-out packaging structure. Background technique [0002] Wafer Level Packaging (WLP) technology is a technology in which the entire wafer is packaged and tested and then cut to obtain a single finished chip. The packaged chip size is exactly the same as the bare chip. Wafer-level chip size packaging technology has completely subverted traditional packaging such as Ceramic Leadless Chip Carrier and Organic Leadless Chip Carrier. It conforms to the market’s increasing demand for microelectronic products. Small, short, thin and low price requirements. The chip size after wafer-level chip size packaging technology has reached a high degree of miniaturization, and the chip cost has been significantly reduced as the chip size decreases and the wafer size increases. Wafer-level chip size packaging technology is a technology that integrates IC design, wafer manufacturi...
Claims
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Login to View More IPC IPC(8): H01L25/16H01L23/495H01L23/31
CPCH01L24/18H01L2224/24195H01L21/568H01L24/96H01L2224/04105H01L2224/12105H01L2924/1815H01L2924/3511H01L2224/19H01L2924/00H01L2924/00012
Inventor 陶玉娟石磊沈海军
Owner NANTONG FUJITSU MICROELECTRONICS