III-V family semiconductor MOS (Metal Oxide Semiconductor) interface structure

Abstract

The invention discloses an III-V family semiconductor MOS (Metal Oxide Semiconductor) interface structure which comprises a monocrystal substrate (101), a buffer layer (102), a quantum well bottom barrier layer (103), a high-mobility quantum well channel (104), a gallium phosphide interface control layer (105), a high-k gate dielectric (106) and a metal gate structure (107), wherein the buffer layer (102) is formed on the upper surface of the monocrystal substrate (101); the quantum well bottom barrier layer (103) is formed on the buffer layer (102); the high-mobility quantum well channel (104) is formed on the quantum well bottom barrier layer (103); the gallium phosphide interface control layer (105) is formed on the high-mobility quantum well channel (104); the high-k gate dielectric (106) is formed on the gallium phosphide interface control layer (105); and the metal gate structure (107) is formed on the high-k gate dielectric (106). The MOS (Metal Oxide Semiconductor) interface structure disclosed by the invention which adopts gallium phosphide as the interface control layer has the advantages of realizing high carrier mobility and low interface state density at the same time and meeting the requirements of a high-performance III-V family semiconductor MOS (Metal Oxide Semiconductor) technology with.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, in particular to a III-V group semiconductor MOS interface structure with high carrier mobility and low interface state density. Background technique [0002] The existing silicon integrated circuit technology follows Moore's law to improve performance by reducing the feature size, which will inevitably bring about the complexity of process equipment and manufacturing technology, especially when semiconductor technology develops to the nanometer scale, silicon integrated circuit technology is increasingly approaching its theory Due to the dual limits of technology and technology, using high-mobility channel materials to improve the performance of silicon-based CMOS technology has become an important direction for the continuation of Moore's Law. The room temperature electron mobility of III-V semiconductor materials is about 6-60 times that of silicon, and i...

AI Technical Summary

Problems solved by technology

However, growing high-k gate dielectric materials directly on the surface of high-mobility channels will bring about problems such as the decrease of channel carrier mobility, high interface state density, and reliability of MOS interfaces.

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