Fabrication method of semiconductor structure

A manufacturing method, semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of consumption, time and production costs, etc., to save time and cost, reduce photolithography The number of times, the effect of guaranteed performance

Active Publication Date: 2011-11-30
CSMC TECH FAB2 CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Since the formation of the opening 108 and the opening 110 requires two photo

Method used

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  • Fabrication method of semiconductor structure
  • Fabrication method of semiconductor structure
  • Fabrication method of semiconductor structure

Examples

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Example Embodiment

[0028] In the process of forming the pad and the fuse structure, in order to improve the reliability of the device, it is usually necessary to perform two photolithography and etching processes, one is to protect the fuse area with photoresist, and the protective layer in the pad area An opening is formed in the fuse area to expose the solder pad, and then the photoresist in the fuse area is stripped; the other time, the photoresist is used to protect the solder pad area, forming an opening in the protective layer of the fuse area, and leaving part of the protective layer on The fuse structure is used for subsequent laser repair, and then the photoresist in the pad area is stripped off. Since two photolithography needs to be performed and two photomasks are used, more time and production costs are required.

[0029] In view of the above-mentioned problems, the present invention forms the pattern of the solder pad and the fuse structure on the same mask plate at the same time afte...

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PUM

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Abstract

The invention discloses a semiconductor structure manufacturing method, which comprises the following steps of: providing a substrate, wherein the substrate is divided into a fuse region with a fuse structure and a bonding pad region with a bonding pad, the fuse structure comprises a first anti-etching layer on a surface layer and the bonding pad comprises a second anti-etching layer on the surface layer; forming a protective layer; forming a photoresist layer on the protective layer, patterning the photoresist layer and forming an opening in the photoresist layer, wherein the opening exposesthe protective layer at a part of a bonding pad position, at a fuse structure position and on the two sides of the fuse structure position; performing primary etching until the first anti-etching layer of the fuse region and the second anti-etching layer of the bonding pad region are exposed at the same time; and performing secondary etching to remote the second anti-etching layer on the surface layer of the bonding pad and the first anti-etching layer on the surface layer of the fuse structure. In the method, a process of performing single photoetching and then sequentially performing the primary and secondary etching is adopted to reduce photoetching times.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a method for manufacturing a pad and a fuse structure. Background technique [0002] With the improvement of semiconductor technology level and the increase of the complexity of integrated circuits, semiconductor components are more susceptible to various defects, and the failure of a single component such as a transistor or a memory unit often leads to functional defects of the entire integrated circuit. A common solution is to form some fusible connection lines in the integrated circuit, that is, fuse structures, so as to ensure the availability of the integrated circuit. [0003] Generally speaking, the fuse structure is used to connect redundant circuits in integrated circuits. When a defect occurs in the circuit, the fuse is blown, and the redundant circuit is used to repair or replace the defective circuit. The fuse structure is often used in memory. When the produc...

Claims

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Application Information

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IPC IPC(8): H01L21/02H01L21/60H01L23/525H01L23/485
CPCH01L24/05H01L2224/02166H01L2924/14H01L2924/00
Inventor 牛建礼赵金强周国平杨瑞
Owner CSMC TECH FAB2 CO LTD
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