Method for manufacturing semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises the steps of: preparing a semiconductor chip, and sequentially forming an etching stopping layer, an interlayer dielectric layer and a patterned photoresist layer on the top layer of the semiconductor chip; etching the interlayer dielectric layer by taking the photoresist layer as a mask until the etching stopping layer is exposed in a first process reaction cavity (401A); delivering the semiconductor chip to a second process reaction cavity (401B); removing the photoresist layer in the second process reaction cavity (401B); delivering the semiconductor chip back to the first process reaction cavity (401A); and etching the etching stopping layer by taking the etched interlayer dielectric layer as a mask in the first process reaction cavity (401A). According to the method for manufacturing the semiconductor device, residual fluorine from etching treatment can be prevented from damaging a low-k material layer in subsequent treatment, so that the shape of a channel profile is improved and the electrical performance of the semiconductor device is increased.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a process capable of improving the profile of a trench in an interlayer dielectric (ILD) made of a low-k material. Background technique [0002] Currently, the plasma etching process is widely used as a semiconductor manufacturing process to define the structure of silicon integrated circuits. In the copper interconnection process, since copper is difficult to etch, the plasma etching process is usually used to etch through holes or trenches in the interlayer dielectric layer (ILD) to fill the metal into it to achieve conductive interconnection ( Damascus Law). Generally, ILDs are composed of silica-based materials. [0003] As IC manufacturing moves to sub-45nm and below, interconnect delay becomes a major limiting factor in increasing the speed and performance of integrated circuits (ICs). It is well known that one of the ways to minimize inte...

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Problems solved by technology

exist Figure 3C shows the trench profile formed by stripping the PR mask layer under low pressure after the etching process. effect" resulting in top rounding of the trench sidewalls in the low-k material layer

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