Method for controlling critical size of graph on uneven silicon slice surface

Abstract

The invention relates to a method for controlling a critical size of a graph on an uneven silicon slice surface, which comprises the following steps that: establishing a relation curve of a step height and the critical size, and the step height is a distance between a highest point and a lowest point on the surface of a silicon slice; measuring a real step height; judging whether the real step height is equal to a setup value, if the real step height is equal to the setup value, exposing photosensitive resist according to a setup exposure energy, and if the real step height is not equal to the setup value, executing a next step; utilizing a formula Esplit= Ebaseline + (CDsplit - CDBASELINE) * Slop to calculate the exposure energy, exposing the photosensitive resist according to the calculated exposure energy Esplit, wherein the Esplit indicates the real exposure energy, Ebaseline indicates the setup exposure energy, CDsplit is a critical size corresponding to the real step height in the relation curve of the step height and the critical size, CDbaseline is a critical size corresponding to the step height setup value in the relation curve of the step height and the critical size, and Slop is a constant.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a method for controlling the critical dimension of graphics on the surface of an uneven silicon chip. Background technique [0002] The purpose of photolithography is to copy the pattern on the photomask to the surface of the silicon wafer. The CD (critical dimension) of the pattern copied to the surface of the silicon wafer must meet the process requirements, otherwise, the silicon wafer cannot enter the subsequent process flow. [0003] Taking the TIM (tunnel implant mask) layer as an example, briefly introduce the photolithography process: [0004] Such as Figure 1A As shown, a barrier layer 102 is formed on the substrate 101, and the barrier layer 102 is usually a silicon nitride layer; [0005] Such as Figure 1B As shown, a trench 103 is etched on the substrate 101; [0006] Such as Figure 1C As shown, a deposited oxide 104 fills the trench 103; [0007] Such...

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Problems solved by technology

[0016] (2) In the same batch of silicon wafers, the critical dimension CD of the pattern of the tunneling injection mask layer of different silicon wafers may be different, such as image 3 as shown ( image 3 The exposure energy of each silicon wafer in is the same, the ordinate indicates the size of the critical dimension CD of the tunneling injection mask layer, and the abscissa is used to mark the silicon wafer, for example, #1 indicates the first silicon wafer in a batch, #2 Indicates the second silicon wafer in the same batch, ..., and so on), from image 3 It can be seen that for different silicon wafers of the same batch, the critical dimension of the tunneling implantation mask layer sometimes varies greatly. For example, the critical dimension of the tunneling implantation mask layer of the fifth silicon wafer is 0.61 μm, while The critical dimension of the tunneling implant mask layer of the tenth silicon wafer is 0.653 μm, which means that the critical dimension CD of the tunnel implant mask layer of some silicon wafers in a batch of silicon wafers does not meet the process requirements

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