Method for forming small-spacing pattern

Abstract

The invention provides a method for forming a small-spacing pattern. The method comprises the following steps of: providing a front-end device structure which comprises a lower-layer structure, a first ultralow-dielectric-constant material layer and a photoinduced resist layer; taking the photoinduced resist layer as a mask and etching the first ultralow-dielectric-constant material layer; carrying out ashing treatment on plasma so as to remove the photoinduced resist layer and simultaneously lead the plasma to react with the inner side of the pattern at an opening of the first ultralow-dielectric-constant material layer; forming a second ultralow-dielectric-constant material layer; flattening the second ultralow-dielectric-constant material layer; and carrying out wet-process cleaning soas to remove the part of the first ultralow-dielectric-constant material layer reacting with the plasma. In the method, the problem in the prior art due to the use of PR (photoinduced resist) masks or hard masks without consistent heights can be solved, and the pattern with the spacing being less than or equal to 32nm can be formed by once photoetching and once-to-twice etching process, so that the production cycle can be shortened greatly and the manufacturing cost can be reduced.

Description

technical field [0001] The present invention relates to a method for fabricating a semiconductor device, and in particular, to a method for forming fine-pitch patterns. Background technique [0002] During the manufacture of semiconductor devices, various individual processes need to be applied, for example, photolithography, deposition, etching, cleaning processes, and the like. Currently, as the integration of constituent elements in semiconductor devices increases, the layout design rules of such elements gradually shrink and their tolerances become extremely strict, and the shrinking design rules require, for example, patterns used in photolithography processes spacing is reduced. The shrinking of design rules and pattern spacing began to challenge the resolution accuracy of conventional lithography equipment. In fact, the resolution accuracy required by the design rules in use today has exceeded the accuracy that some conventional process equipment can provide. [000...

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Problems solved by technology

[0012] However, in the above-mentioned method for forming small-pitch patterns according to the prior art, the bottom section of the photoresist layer presents an uneven topography due to the unevenness of the surface of the bottom anti-reflection layer located between two adjacent patterns, This will affect the critical dimension (CD) of the pattern formed by subsequent etching in the hard mask layer

Moreover, when the underlying structure 102 is finally etched, a part of the area uses a double-layer hard mask composed of the first hard mask layer 103 and the second hard mask layer 104, while another part of the area uses the first hard mask layer 103. The single-layer hard mask formed by the hard mask layer 103 makes the height of the mask inconsistent in each region, such as Figure 1D As shown in , which in turn will also lead to inconsistencies in the height of the pattern formed in the underlying structure 102

In addition, the method according to the prior art requires two photolithography and three times of etching to form a small-pitch pattern in the underlying structure 102, and the two photolithography requires the use of two reticle with different opening patterns, so it is extremely difficult. Greatly increased manufacturing costs

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