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Method for making longitudinal region of super junction device

A super-junction, vertical technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of monocrystalline silicon residue, affecting device characteristics, device leakage or breakdown voltage reduction, etc., to avoid device defects, The effect of improving device performance

Active Publication Date: 2013-12-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Finally, after the CMP barrier layer 21 is removed, some protruding single crystal silicon residues will be formed, which will become defects and affect the characteristics of the device (such as causing device leakage or a decrease in breakdown voltage)

Method used

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  • Method for making longitudinal region of super junction device
  • Method for making longitudinal region of super junction device
  • Method for making longitudinal region of super junction device

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Embodiment Construction

[0031] Taking the PMOS-based super junction MOS transistor as an example, the method for manufacturing the vertical region of the super junction device of the present invention is introduced, including the following steps:

[0032] Step 1, see Figure 2a , growing a lightly doped N-type epitaxial layer 11 on the heavily doped N-type silicon substrate 10 . The resistivity of the epitaxial layer 11 is, for example, 0.1 to 10 ohm·μm.

[0033] Step 2, see Figure 2b , depositing a CMP barrier layer 21 and an etch barrier layer 23 sequentially on the epitaxial layer 11 .

[0034] In one embodiment, the CMP barrier layer 21 is, for example, silicon oxide, using a CVD (Chemical Vapor Deposition) process or a thermal oxidation growth process, with a thickness of preferably The etch barrier layer 23 is, for example, silicon oxide, using APM or CVD process, with a thickness of As a barrier layer when etching trenches. Further, an intermediate barrier layer 22 is further include...

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Abstract

The invention discloses a method for making a longitudinal region of a super junction device. Compared with the prior art, the method comprises the following steps of: firstly, horizontally back-etching a chemical mechanical polishing (CMP) barrier layer after being subjected to a CMP process to make monocrystal silicon under the CMP barrier layer exposed; secondly, removing the exposed monocrystal silicon by isotropic etching; and finally, obtaining the longitudinal region of the monocrystal silicon, which is not provided with horizontal filling. With the adoption of the method, the defect of the device is overcome, and the performance of the device is improved.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a super junction (Super junction) device. Background technique [0002] Super junction MOS transistors have the advantages of high voltage resistance, low on-resistance, low power consumption, and low switching time, and are suitable for high-voltage, high-current, and high-power applications such as automotive electronics, operational amplifiers, and power management. [0003] see figure 1 , which is a schematic diagram of the basic structure of a super junction MOS transistor. A layer of lightly doped N-type epitaxial layer 11 is grown on heavily doped N-type silicon substrate 10 , and there is a P-type vertical region 12 in the epitaxial layer 11 . The P-type vertical region 12 is up against the upper surface of the epitaxial layer 11 , and down to the inside of the epitaxial layer 11 or the interface between the epitaxial layer 11...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/311H01L21/306
Inventor 王雷程晓华刘鹏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP