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Thin film transistor array substrate

A thin-film transistor and array substrate technology, which is applied in the field of thin-film transistor array substrates, can solve the problems of unfavorable production capacity increase, process time increase, multiple laser irradiation times, etc., and achieve the effect of good component characteristics and high carrier mobility

Active Publication Date: 2012-07-04
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] However, in the above-mentioned TDX laser crystallization technology, since the laser beam is irradiated on the amorphous silicon layer on the substrate, and the substrate is moved for scanning operation in the TDX laser crystallization method, the substrate can only be moved no more than two times each time the substrate is moved. 1 / 1 of the laser irradiated area of ​​the substrate
Therefore, when scanning in one direction by the TDX laser crystallization method, not only more laser shots are required, but also the total number of times to move the substrate is increased. In this way, although high-quality polysilicon can be obtained Membrane, but due to the increase of process time, it is not conducive to the improvement of production capacity
In addition, a single scanning pitch is used on the moving substrate or mask. Although the polysilicon in different regions on the substrate is the same, more laser shots are required, and the total number of times to move the substrate or mask is also less. In this way, although the polysilicon film with uniform quality can be obtained, that is, the main grain boundaries of polysilicon at all positions on the substrate are uniformly distributed, but the increase in process time on the substrate is not conducive to the improvement of production capacity.

Method used

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  • Thin film transistor array substrate
  • Thin film transistor array substrate
  • Thin film transistor array substrate

Examples

Experimental program
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Effect test

no. 1 example

[0061] Figure 1A is a schematic diagram of a thin film transistor array substrate according to an embodiment of the present invention, and Figure 1B for Figure 1A Schematic cross-section along section lines AA, BB and CC. Please also refer to Figure 1A and Figure 1B , the thin film transistor array substrate 200 includes a substrate 210, a plurality of polysilicon islands 220 disposed on the substrate 210, and a plurality of gates 230, wherein the substrate 210 is mainly divided into a display area 210D, a gate driving area 210G, and a source driving area 210S, and the polysilicon island 220 includes a plurality of first polysilicon islands 220A and a plurality of second polysilicon islands 220B, the first polysilicon islands 220A are disposed in the display area 210D and the gate driving area 210G, and the second The polysilicon island 220B is disposed in the source driving region 210S.

[0062] Please continue to refer to Figure 1B Each polysilicon island 220A, 220B...

no. 2 example

[0082] Figure 5A is the thin film transistor array substrate of the second embodiment of the present invention along Figure 1A The cross-sectional schematic diagram of the AA, BB, CC section lines. Please refer to Figure 5A , to simplify the description, the above-mentioned components similar to those described above will not be described again. Compared with the previous embodiments, the second polysilicon island 320B of the thin film transistor array substrate 300 of this embodiment has a main grain boundary MGB and a secondary grain boundary SGB, and the main grain boundary MGB of the second polysilicon island 320B is only located In the source region 222 and / or the drain region 224 , in other words, there is no main grain boundary MGB in the channel region 226 of the second polysilicon island 320B. The formation positions of the main grain boundary MGB and the secondary grain boundary SGB of the second polysilicon island 320B can be controlled, for example, by adjusti...

no. 3 example

[0086] Figure 6A is the thin film transistor array substrate of the third embodiment of the present invention along Figure 1A The cross-sectional schematic diagram of the AA, BB, CC section lines. Please refer to Figure 6A , to simplify the description, the above-mentioned components similar to those described above will not be described again. Compared with the second embodiment, the main grain boundary MGB of the second polysilicon island 420B of the thin film transistor array substrate 400 of this embodiment is only located in the source region 222 and / or the drain region 224, in other words, the second most There is no main grain boundary MGB in the channel region 226 of the silicon island 420B. Moreover, in this embodiment, the grain size in the second polysilicon island 420B of the thin film transistor array substrate 400 is substantially smaller than the grain size in the first polysilicon film.

[0087] Figure 6B It is a diagram showing the crystal grain arrang...

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Abstract

The invention provides a thin film transistor array substrate, which comprises a substrate, a plurality of polycrystalline silicon islands and a plurality of grids, wherein the substrate is provided with a display region, a grid driving region and a source driving region; the polycrystalline silicon islands are configured on the substrate; each polycrystalline silicon island is provided with a source region and a drain region, and a channel region positioned between the source region and the drain region; the polycrystalline silicon islands comprise a plurality of first polycrystalline silicon islands and a plurality of second polycrystalline silicon islands; the first polycrystalline silicon islands are configured in the display region and the grid driving region; the first polycrystalline silicon islands are provided with primary crystal boundaries and secondary crystal boundaries; the primary crystal boundaries of the first polycrystalline silicon islands are only positioned in the source regions and / or the drain regions; the second polycrystalline silicon islands is configured in the source driving region; the grain sizes in the first polycrystalline silicon islands are different from the grain sizes in a second polycrystalline silicon film; and the grids are configured on the substrate, and correspond to the channel regions.

Description

[0001] This patent application is a divisional application of a Chinese patent application with an application date of September 19, 2008, an application number of 200810161502.7, and an invention title of "Thin Film Transistor Array Substrate and Manufacturing Method". technical field [0002] The present invention relates to a semiconductor element array substrate and a manufacturing method of the semiconductor element array substrate, and in particular to a thin film transistor array substrate and a manufacturing method of the thin film transistor array substrate. Background technique [0003] In recent years, with the increasing maturity of optoelectronic technology and semiconductor manufacturing technology, flat-panel displays have flourished. Among them, liquid crystal displays have gradually replaced traditional cathodes based on their advantages of low-voltage operation, no radiation scattering, light weight, and small size. Ray tube displays have become the mainstre...

Claims

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Application Information

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IPC IPC(8): H01L27/02H01L29/786H01L29/04H01L21/77
Inventor 孙铭伟赵志伟
Owner AU OPTRONICS CORP