Low-voltage high-speed frequency divider

A frequency divider, low-voltage technology, applied in the direction of electrical components, automatic power control, etc., can solve the problems of reducing the minimum value of the power supply voltage of the frequency divider, complex circuit structure, etc.

Inactive Publication Date: 2012-07-04
杭州中科微电子有限公司
View PDF2 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] The purpose of the present invention is to overcome the very complex defects of the technology and circuit structure of the prior art, disclose a kind of high-speed, low-voltage high-speed frequency divider, its circuit structure is comparatively simple, and it is b

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Low-voltage high-speed frequency divider
  • Low-voltage high-speed frequency divider
  • Low-voltage high-speed frequency divider

Examples

Experimental program
Comparison scheme
Effect test

Example

[0076] The first embodiment

[0077] The composition of the basic circuit structure of the low-voltage high-speed frequency divider of the present invention is as follows: Figure 2a Shown. The low-voltage high-speed frequency divider is composed of two identical latches 2-1 and 2-2 cross-coupled with clocked transistors. The first latch 2-1 with a clocked transistor includes: a sampling differential pair amplifier 21 consists of M 1 And M 2 Composition, latched cross-coupled pair amplifier 22 by M 3 And M 4 It is composed of load tube M as load module 23 P1 , M P2 And clock control tube M C1 composition. The second latch 2-2 with clocked transistor includes: a sampling differential pair amplifier 24 consists of M 5 And M 6 Composition, latched cross-coupled pair amplifier 25 by M 7 And M 8 It is composed of load tube M as load module 26 P3 , M P4 And clock control tube M C2 composition.

Example

[0078] Example 2

[0079] Refer to the tube-level structure composition diagram of another latch 2-1 with low voltage and clocked transistors Figure 2b . The differential signal CN and CP from the front-end VCO or other devices are respectively added to the drain of the tail current source after passing through the blocking capacitor. The differential signal CN is also connected to the source of the sampling differential pair tube 21, and the differential signal CP is also connected to The source of the differential pair tube 22 is latched. The differential signal input terminals of the sampling differential pair tube 21 of the latch 2-1 with clocked transistor are IP and IN, the cross-coupled output terminals of the latched cross-coupled tube 22 are QP and QN, and the cross-coupled output terminal QP and QN is connected to load module 23 clock control tube MC in parallel 1 Source and drain of load module 23 Z 1 And Z 2 Load tube, load tube Z 1 ,Z 2 And clock control tube MC 1 ...

Example

[0080] Example 3

[0081] Such as image 3 The circuit diagram of the low-voltage high-speed frequency divider of the third embodiment is given. The low-voltage high-speed frequency divider includes a first latch 3-1 and a second latch 3-2. The first latch consists of M 1 And M 2 The sampled differential pair 31 and M 5 And M 6 Latched cross-coupled pair 32 composed of MP 1 , MP 2 And clock control tube MC 1 The composed load module 33 also includes the first tail current source. The second latch consists of M 5 And M 6 Composed of sampling differential pair tube 34, and by M 7 And M 8 Latched cross-coupled pair 35 composed of MP 3 , MP 4 And clock control tube MC 2 The composed load module 36 also includes a second tail current source. image 3 In, amplifier M 1 ~M 8 All are NMOS tubes, MP in the load module 1 ~MP 4 And clock control tube MC 1 ~MC 2 All are PMOS tubes. The clock signal CP passes through the DC blocking capacitor C 1 M added to sampled differential pair 31 1 ~M 2...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a low-voltage high-speed frequency divider. A clock control tube is arranged at two ends of load output so as to form a low-supply-voltage frequency divider with clock-controlled transistors. Compared with the circuit structure of the conventional frequency divider, the low-voltage high-speed frequency divider does not need a clock input differential pair tube, and reduces the limitation on the minimum value of a supply voltage. The low-voltage high-speed frequency divider comprises two latches with the same circuit structure, wherein a clock-controlled transistor which is controlled by same-direction clock signals is connected to two output ends of each latch respectively; and the dynamic load of each latch with the clock-controlled transistor is low in resistance in a sampling stage to reduce charging and discharging time, so that the conversion speed is greatly increased, the working frequency is increased, the defect that a quiescent bias point of the conventional dynamic load structure changes is overcome, and the dynamic load is high in resistance value in a latching stage to provide enough gains. One more control dimension is added to the low-voltage high-speed frequency divider, and compared with the conventional latch, the low-voltage high-speed frequency divider is higher in working frequency and wider in working range, and is more adaptive to a low supply voltage.

Description

[0001] Field [0002] The invention belongs to the technical field of integrated circuit signal processing, and relates to a frequency divider with a clock-controlled transistor, in particular to a low-voltage high-speed frequency divider, a phase-locked loop for a wireless radio frequency synthesizer and corresponding products. technical background [0003] The source-coupled logic circuit is evolved from the ECL structure of the bipolar circuit. Due to the small swing of the circuit, the working speed of the circuit is improved. Source-coupled logic (SCL) frequency divider occupies an important proportion in high-speed CMOS frequency division circuits due to its advantages of wide operating range and suitable power consumption. The key to limit the speed of the source coupling circuit is the load resistance. A small load resistance is beneficial to reduce the time constant, and a large resistance is beneficial to the amplification of the signal. In order to meet the require...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H03L7/18
Inventor 于云丰潘文光庄海孝马成炎
Owner 杭州中科微电子有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap