Large-scale integrated circuit wiring method based on cloud computing platform and system thereof

Abstract

The invention discloses a large-scale integrated circuit wiring method based on a cloud computing platform and a system thereof, belonging to the field of integrated circuit design. In the invention, the wiring problem is divided into local sub-problems according to the area in the detailed wiring and design rule checking and correcting processes, and the sub-problems are distributed to a computer cluster at a cloud end to be solved. Through the invention, the detailed wiring and design rule checking problem of a very-large scale integrated circuit of 65nm and below can be quickly and effectively handled. Meanwhile, the invention provides a new data organization mode of detailed wiring, which can minimize the data transmission flow of cloud-end computers and improve the computing efficiency without increasing the communication cost of clusters.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the technical category of integrated circuit design optimization under the integrated circuit manufacturing process with the line width of the interconnection line at or below 65nm. Background technique [0002] The integrated circuit is designed by the designer with the help of electronic design automation (EDA) tools to design the integrated circuit layout, delivered to the integrated circuit manufacturer, through the circuit mask preparation (Mask), and the wafer (Wafer) for oxidation, doping, photolithography A series of manufacturing processes such as transferring the circuit mask to the wafer, so as to realize its circuit function. For digital circuit design, the layout design process includes steps such as behavioral synthesis, logic synthesis, physical design and layout optimization. Among them, physical design is the most time-consuming step and has the greatest...

AI Technical Summary

Problems solved by technology

Due to the reduction of the feature size, the number of transistors that can be accommodated on the chip has increased accordingly, and the scale and complexity of the circuit design have also continued to increase; on the other hand, the manufacturing process nodes of 65nm and below have appeared Crosstalk coupling, complex design rule checking, post-routing manufacturability optimization and other new issues

Due to the limitations of computing power and computing resources, traditional routing tools have been difficult to meet the requirements of dealing with these large-scale and complex problems

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