Grid optimization method for through silicon via (TSV) positions in automatic layout of three-dimensional (3D) integrated circuit

Abstract

The invention discloses a grid position optimization method for through silicon vias (TSVs) in a three-dimensional (3D) integrated circuit, and belongs to the field of 3D integrated circuit designs. When the 3D integrated circuit is produced and manufactured, a manufacturer cannot process a layout in which intervals among the TSVs are smaller than interval constraint of a processing technology. According to the invention, the grid method is used to optimize the intervals among the TSVs, so that an optimized layout is obtained and the intervals among the TSVs satisfy the technological processing requirement and the manufacturing can be completed. The method disclosed by the invention is implemented according to the steps as follows: firstly, a rectangular coordinate system is established in a layout initially set for the TSVs; afterwards, coordinates of the TSVs are determined, then a grid is produced and the distance between every two grid points in the grid is guaranteed to be larger than the minimum distance capable of being technologically processed; next, each TSV is moved to a closest grid point; and finally, the phenomena that multiple TSVs exist on a single point are arranged to guarantee that only one TSV exists on each grid point of the final layout, then the optimization is completed and the integrated circuit is produced and manufactured.

Description

field of invention [0001] The present invention generally relates to the design and manufacture of 3D integrated circuits, and more specifically, the present invention relates to a method for automatic layout in 3D integrated circuit design, which belongs to the field of circuit design. Background technique [0002] An integrated circuit (integrated circuit) is a tiny electronic device or component. Using a certain process, the transistors, diodes, resistors, capacitors, inductors and other components required in a circuit are interconnected together, fabricated on a small or several small semiconductor wafers or dielectric substrates, and then packaged in a tube. Inside the shell, become a microstructure with the desired circuit function. Today, with the rapid development of integrated circuits, hundreds of millions of transistors can be integrated on a single chip. More specifically, according to the description of Moore's Law, the advanced technology level has reached t...

AI Technical Summary

Problems solved by technology

However, due to the constraints of the 2D integrated circuit structure on the plane, as the circuit develops towards a smaller, denser and more efficient direction, there are many difficult problems in the planar 2D integrated circuit, such as the delay of the chip caused by too long lines.

Images