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Semiconductor detection structure, as well as forming method and detection method thereof

A technology for detecting structures and semiconductors, applied in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as waste of resources, damage to chips, etc., and achieve the effect of low manufacturing cost

Active Publication Date: 2015-04-01
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, in the prior art, the chip is usually tested after the chip is packaged. The above-mentioned detection method can only determine whether the chip is invalid, and cannot obtain whether the device under the pad in the chip is damaged due to wire bonding The information that is damaged, and the use of scanning electron microscope analysis to detect the chip will destroy the chip, resulting in a waste of resources

Method used

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  • Semiconductor detection structure, as well as forming method and detection method thereof
  • Semiconductor detection structure, as well as forming method and detection method thereof
  • Semiconductor detection structure, as well as forming method and detection method thereof

Examples

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no. 1 example

[0040] The first embodiment of the present invention provides a method for forming a semiconductor detection structure, please refer to figure 2 , including the steps: step S101, providing a semiconductor substrate; step S102, forming an ion-doped region in the semiconductor substrate, the ion-doped region including a first region and a second region; step S103, in the ion-doped A gate oxide layer and a gate are sequentially formed on the surface of the first region of the region; Step S104, a dielectric layer is formed on the surface of the gate and the ion-doped region; Step S105, a first conductive plug is formed in the dielectric layer, and the first The conductive plug communicates with the second region of the ion-doped region; Step S106, forming a first metal layer on the surface of the dielectric layer on the first region; Step S107, forming an isolation layer on the surface of the first metal layer and the dielectric layer , forming a second conductive plug in the is...

no. 2 example

[0077] The second embodiment of the present invention provides a method for forming another semiconductor detection structure, including the following steps: step S201, providing a semiconductor substrate; step S202, forming an ion-doped region in the semiconductor substrate, the ion-doped region includes The first region and the second region; step S203, sequentially forming a gate oxide layer and a gate on the surface of the first region of the ion-doped region; step S204, forming a dielectric layer on the surface of the gate and the ion-doped region; step S205, forming a first conductive plug in the dielectric layer, the first conductive plug communicates with the second region of the ion-doped region; step S206, forming a first metal layer on the surface of the dielectric layer on the first region, Forming a first test metal layer on the surface of the first conductive plug and the dielectric layer; step S207, forming an isolation layer on the surface of the first metal lay...

no. 3 example

[0088] The third embodiment of the present invention provides a method for forming another semiconductor detection structure, including the following steps: step S301, providing a semiconductor substrate; step S302, forming an ion-doped region in the semiconductor substrate, the ion-doped region includes The first region and the second region; step S303, sequentially forming a gate oxide layer and a gate on the surface of the first region of the ion-doped region; step S304, forming a dielectric layer on the surface of the gate and the ion-doped region; step S305, forming a first conductive plug in the dielectric layer, the first conductive plug communicates with the second region of the ion-doped region; step S306, forming a first metal layer on the surface of the dielectric layer on the first region, Form a first test metal layer on the surface of the first conductive plug and the dielectric layer; step S307, form an isolation layer on the surface of the first metal layer, the...

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Abstract

The invention provides a semiconductor detection structure, as well as a forming method and a detection method thereof. The semiconductor detection structure comprises a semiconductor substrate, an ion doping area positioned in the semiconductor substrate, a gate oxide layer and a grid electrode which are sequentially positioned on the semiconductor substrate surface of the first region of the ion doping area, a dielectric layer positioned in the ion doping area and the grid electrode surface, a first metal layer positioned on the surface of the dielectric layer, an isolation layer positioned on the first metal layer and the dielectric layer surface, a solder plate positioned on the surface of the isolation layer, and a test structure positioned on the surface of the second region of the ion doping area, wherein the ion doping area comprises the first region and the second region; and the solder plate and the first metal layer are electrically connected by utilizing a conductive structure. According to the invention, the stress action of a device under the solder plate in a lead linkage process can be detected directly, and the influence of lead linkage to the actual device under the solder plate can be known by detecting whether the first metal layer is deformed or not.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a semiconductor detection structure, a forming method and a detection method thereof. Background technique [0002] With the rapid development of Ultra Large Scale Integration (ULSI), the manufacturing process of integrated circuits has become more and more complex and refined. In order to meet the process requirements, more and more devices need to be formed in smaller and smaller areas, but in the traditional chip circuit wiring structure, active devices are usually not arranged under the chip pads, which will waste a certain chip area . Because the pad is used to connect the active circuit of the chip to the external circuit by bonding with the wire connected to the external circuit. However, several methods of wire bonding such as thermocompression bonding, ultrasonic bonding, and thermosonic ball bonding will exert pressure on the pad, accompanied by thermal energy ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L23/58G01R31/28
CPCH01L2224/05
Inventor 甘正浩
Owner SEMICON MFG INT (SHANGHAI) CORP