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A kind of double-bit nrom memory and the method and structure of improving its electron injection efficiency

An electron injection and bit storage technology, applied in the field of microelectronics, which can solve problems such as crosstalk, increase storage density, and affect the reading of stored data.

Active Publication Date: 2015-08-26
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method improves the storage density, since the charges are stored in the same layer, the charges stored at both ends have a horizontal distribution
Therefore, when the size of the device continues to decrease, crosstalk is prone to occur between the two bits of data stored separately, which affects the reading of the stored data, so it is difficult to further increase the storage density

Method used

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  • A kind of double-bit nrom memory and the method and structure of improving its electron injection efficiency
  • A kind of double-bit nrom memory and the method and structure of improving its electron injection efficiency
  • A kind of double-bit nrom memory and the method and structure of improving its electron injection efficiency

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Embodiment Construction

[0024] The present invention will be further described below in combination with principle diagrams and specific operation examples.

[0025] to combine Figure 4 and Figures 5A-5E Shown, a kind of method of improving double-bit storage NROM electron injection efficiency of the present invention comprises the following steps:

[0026] S1: Prepare a substrate 1, wherein the surface of the substrate 1 has two convex surfaces 10;

[0027] S2: sequentially forming a tunneling dielectric layer 2, a charge storage layer 3, and a blocking oxide layer 4 on the surface of the substrate 1, and the surfaces of the tunneling dielectric layer 2, the charge storage layer 3, and the blocking oxide layer 4 have a convex structure;

[0028] In this step, a tunneling dielectric layer 2 is first deposited on the surface of the substrate 1, the surface of the tunneling dielectric layer 2 includes two first convex structures 20, the first convex structures 20 are located on the convex surface 1...

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Abstract

The invention discloses a method for increasing an electron injection efficiency of a dual bit storage NROM (nitride read only memory), wherein the method comprises the following stepsof preparing a substrate with two convex surfaces; forming a tunneling dielectric layer with a convex surface structure, a charge storage layer and an oxidization barrier layer on the substrate in sequence; preparing polycrystalline silicon on the oxidization barrier layer; carrying out an etching process on the substrate so as to remove the redundant polycrystalline silicon, oxidization barrier layer, charge storage layer and tunneling dielectric layer from the substrate; and forming a source and a drain on two sides of the substrate, and forming sidewalls on the source and the drain. The invention also provides a structure for increasing the electron injection efficiency of the NROM, wherein the structure is prepared with the method; and the invention also provides the dual bit storage NROM which comprises the structure for increasing the electron injection efficiency of the NROM. Hot electrons can be injected into the charge storage layer in a convex surface area, and the impact of a highfield of the drain or the source on the hot electrons can be reduced, so that the injection efficiency of the hot electrons can be increased.

Description

technical field [0001] The invention relates to the field of microelectronics, in particular to a double-bit NROM memory and a method and structure for improving its electron injection efficiency. Background technique [0002] With the rapid development of traditional CMOS VLSI technology, flash memory technology is also developing towards low power consumption, low operating voltage and high storage density. In the past, the polysilicon of the floating gate was used as the charge storage layer. Since the charge stored in the polysilicon floating gate is continuously distributed, when there is a leakage channel, the charge stored on the entire floating gate will be lost through this leakage channel. , so the biggest obstacle limiting the ability of flash memory to scale down is that the thickness of its tunneling oxide layer cannot be continuously reduced, because in the case of thin tunneling oxide layer, direct tunneling and stress-induced leakage current will control the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/792H01L29/423
Inventor 田志顾经纶
Owner SHANGHAI HUALI MICROELECTRONICS CORP