Fabrication method of metal interconnection structure
A technology of metal interconnection structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems such as difficulties in the manufacture of metal interconnection structures
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Embodiment 1
[0061] Specific as figure 1 As shown, a semiconductor substrate 11 is provided, on which a dielectric layer 10 and a mask layer 20 having small-sized through holes are formed. In the figure, only two through holes 1a, 1b are drawn in the mask layer 20 for brief description. In practice, the mask layer 20 may have some through holes arranged in an array, and its diameter width and spacing are: 22nm, 23nm, 32nm, etc. are smaller than the minimum precision that the lithography machine can achieve. When forming the through holes in the mask layer 20, the size that can be achieved by general photolithography can be reduced by using the double pattern exposure technology, so as to form the through holes with small diameter width and pitch in this embodiment. In this embodiment, the diameter width of the through holes 1a and 1b is 22nm, and the distance between them is 22nm.
[0062] In this embodiment, a metal interconnection structure consisting of two contact holes and a trench...
Embodiment 2
[0072] In this embodiment, a structure formed by intersecting two-dimensional lines is used as a mask layer to form the structure to be formed in the present invention, and the structure includes a metal interconnection structure of a contact hole and a trench.
[0073] provide as Figure 9 As shown in the semiconductor structure, the semiconductor structure includes a semiconductor substrate 100 and a dielectric layer 200 formed on the semiconductor substrate 100 . Wherein, the metal interconnection structure of the present invention will be formed in the dielectric layer 200 later. As an embodiment, there is a first buffer layer 300 on the dielectric layer 200, and a first hard mask layer 400 is formed on the first buffer layer 300. The first hard mask layer 400 is composed of a plurality of lines with a pitch of k Composition, the plurality of lines are arranged in a first pattern. The k is 22nm, 23nm, 32nm, etc., which are smaller than the minimum precision that the phot...
Embodiment 3
[0094] Similar to Embodiment 2, provide such as Figure 9 The semiconductor structure shown, its top view is as Figure 27 shown. In this embodiment, it is necessary to form two metal interconnection structures corresponding to the through-hole patterns circled by the dotted circles in the figure, one of the metal interconnection structures includes a contact hole aligned with the through-hole pattern 31 and a contact hole aligned with the through-hole pattern 34. Aligned contact holes and a trench connecting the two contact holes, another metal interconnection structure including a contact hole aligned with via pattern 33 and a contact hole aligned with via pattern 32 next to via pattern 34 and a groove connecting the two contact holes. Since the through-hole pattern 34 and the through-hole pattern 33 are adjacent to each other, if their corresponding photoresist patterns are to be formed in the same exposure, then in the process of exposure, in the mask plate corresponding...
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