Addressing testing circuit for transistor key parameters and testing method thereof

Abstract

The present invention relates to a method for measuring transistor key parameters, and more particularly, to an addressable test circuit for testing the transistor key parameters, and test method thereof. The saturation current and the leakage current of the transistor are measured by using different measurement signal lines respectively. The addressable test circuit is applied in testing multiple MOS transistors, each MOS transistor having a gate end G, a drain end D, source end S, and a substrate B. The S end and the D end of each MOS transistor are connected to different measurement signal lines respectively. The test circuit of the present invention has high area utilization, and multiple MOS transistors can be placed within a small wafer area; moreover, Idsat and Ioff of each MOS transistor can be both accurately measured.

Description

technical field [0001] The invention relates to a method for measuring key parameters of a transistor, in particular to an addressable test circuit for key parameters of a transistor and a test method thereof. Background technique [0002] With the development of integrated circuits, the feature size of devices has been rapidly reduced, and the performance of circuits has been improved. However, when the process is developed to nanotechnology, it also brings a series of challenges, especially the problem of process volatility. Smaller feature size means that there is less margin for process fluctuations in the manufacturing process, resulting in greater instability of process parameters, such as random fluctuations in temperature, doping concentration, etc., and photolithography, chemical mechanical polishing (CMP), etc. The resulting fluctuations in critical dimensions will lead to large fluctuations in threshold voltage and a sharp increase in leakage current, which not o...

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Problems solved by technology

Its disadvantages are: (1) Here, the PMOS is a thick-oxide device, and the substrate voltage during normal operation is greater than the VDD / GND voltage applied when measuring the DUT subthreshold leakage current. Therefore, even if There is no voltage drop between the source and drain of the PMOS, and there is still a voltage drop between the drain terminal and the substrate, and there will still be a certain leakage; (2) Use a single PMOS as the switching circuit at the D terminal. If you want the leakage current of the switch itself to be small, the switch The on-resistance of the circuit itself will be very large, which will affect the I dsat measurement, so the size of the switching circuit in this approach requires a certain compromise between saturation current and leakage current

[0007] At present, there are many addressable test chips in the industry that can measure the current in the saturation region of MOS transistors. However, since the MOS transistors share the measurement signal line through the addressing circuit and the switching circuit, the accumulated background leakage current (background leakage) of the switching circuit has a great influence on the actual leakage current. The measurement accuracy has a great influence, and it is rare to measure the sub-threshold leakage current, or to accurately measure the saturation current and the sub-threshold leakage current at the same time

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