NMOS (N-channel metal oxide semiconductor) transistor forming method

Abstract

Disclosed is an NMOS (N-channel metal oxide semiconductor) transistor forming method. The method includes: providing a semiconductor substrate; forming an oxide layer on the surface of the semiconductor substrate and forming a polycrystalline silicon layer on the oxide layer; subjecting the semiconductor substrate to first ion implantation, wherein implanted ions are fluoride ions and nitrogen ions; etching the polycrystalline silicon layer and the oxide layer to respectively forming a grid electrode and a grid oxide layer, and forming a lightly doped source or drain region in the semiconductor substrate on two sides of the grid oxide layer and the grid electrode; and forming a side wall on a side wall surface of the grid oxide layer and the grid electrode, forming a heavily doped source or drain region in the semiconductor substrate on two sides of the side wall, and forming an NMOS transistor. The semiconductor substrate is subjected to implantation of the fluoride ions and the nitrogen ions, so that reliability of the grid oxide layer of the NMOS transistor is improved, hot-carrier injection effect in the NMOS transistor is lowered, and TDDB (time dependent dielectric breakdown) characteristics of the grid oxide layer are improved.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a method for forming an NMOS transistor capable of improving the reliability of a gate oxide layer. Background technique [0002] With the continuous improvement of the integration of semiconductor devices, the feature size is gradually reduced, the length of the channel of the MOS transistor is also gradually reduced, and the thickness of the gate oxide layer is also continuously reduced. Since the gate voltage will not continue to decrease (currently at least 1V), so that the electric field strength received by the gate oxide layer becomes larger, time-dependent dielectric breakdown (time dependent dielectric breakdown, TDDB) is more likely to occur, and it is more likely to cause device failure. At the same time, both the input / output devices as the peripheral circuits of the chip and the core devices as the memory require a high driving voltage, which causes the elect...

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Problems solved by technology

However, the above method cannot improve the TDDB characteristics of the gate oxide layer, and may also cause problems such as short channel effect (SCE, Short Channel Effect)

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