Interlayer insulating layer formation method and semiconductor device

Abstract

Provided are: an interlayer insulating layer formation method which enables the formation of an interlayer insulating layer having excellent mechanical strength and moisture absorption resistance and a low dielectric constant; and a semiconductor device having reduced wiring delay. A method for forming an interlayer insulating layer for a semiconductor device by a plasma CVD method comprises the steps of: installing a substrate to a treatment vessel having reduced pressure; supplying a plasma generation gas to a first space (1a) placed apart from the substrate; exciting the plasma generation gas in the first space (1a); and supplying a raw material gas comprising a boron compound having at least a hydrogen group or a hydrocarbon group to a second space (1b) formed between the first space (1a) and the substrate. A semiconductor device wherein multilayer interconnection is achieved through an interlayer insulating layer having an amorphous structure containing boron, carbon and nitrogen formed therein, and wherein a hydrocarbon group or an alkylamino group is allowed to co-exist in an amorphous structure containing hexagonal and cubic boron nitride in the interlayer insulating layer.

Description

technical field [0001] The present invention relates to a method for forming an interlayer insulating layer of a semiconductor device in which multilayer wiring is performed on a substrate by a plasma CVD (Chemical Vapor Deposition) method, and a method for forming an interlayer insulating layer via an interlayer insulating layer. A semiconductor device with multilayer wiring. Background technique [0002] As the interlayer insulating layer of ultra-large-scale integrated circuit (ULSI) with multilayer wiring structure, the existing SiO 2 SiOF, SiCO or organic film as the base material. However, the integration of ULSI has progressed in response to the demand for miniaturization and high performance of electronic devices in recent years, and the wiring delay due to the increase in wiring length exceeds the gate delay which is a characteristic of transistors. In order to solve the problem of wiring delay, it is necessary to reduce the RC time constant of wiring, especially ...

AI Technical Summary

Problems solved by technology

However, in response to the demand for miniaturization and high performance of electronic devices in recent years, the integration of ULSI has continued to advance, and the wiring delay caused by the increase in wiring length exceeds the gate delay that is a characteristic of transistors.

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