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Contact Via Etching Method

A contact through-hole and etching-resistant technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as gate etching loss, achieve the effects of improving performance, reducing exposure processes, and saving manufacturing costs

Active Publication Date: 2015-08-19
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The invention provides a method for etching a contact hole, which solves the problem that the grid is etched and lost when the contact hole is etched in the prior art

Method used

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Embodiment Construction

[0042] The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

[0043] The technical means adopted in the present invention are realized based on the following concepts. In order to solve the existing problems in the prior art after the actual etching of the gate region due to over-etching and load effects when etching contact vias, it is necessary to make the In the same dry contact etching process, the selectivity ratio of the interlayer dielectric isolation layer (ILD) above the gate region is higher than that of the ILD layer on other contact via regions. Further, due to the superiority of DSA technology in photolithography and sub-lithography processes, the inherent period L of the block copolymer 0 By adjusting the number of monomers in the block molecule, L 0 It is adjus...

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Abstract

The invention provides a contact through hole etching method. Due to the fact that a gate etching-resistant layer is formed at the position of a corresponding gate region in an interlevel dielectric isolation layer above the gate region, the gate etching-resistant layer can offset gate region excessive etching caused by interlevel dielectric isolation layers with different thicknesses and on a semiconductor structure gate region and an active region when a gate contact through hole and a sharing contact through hole are etched. The method improves performance of a semiconductor device accordingly. Furthermore, the DSA technology is adopted in the gate etching-resistant layer forming process to form a mask, exposure process times are not increased, and manufacture cost is not increased.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a contact via hole etching method. Background technique [0002] As the device feature size of VLSI continues to shrink and the integration level continues to increase, the requirements for integrated circuit manufacturing processes, such as photolithography, etching, deposition, ion implantation, etc., are more stringent, and small process deviations will lead to device Changes in electrical performance, which in turn cause the overall circuit to deviate from the design value. [0003] In the integrated circuit manufacturing process, for example, after the semiconductor device structure is generated on the substrate, it is necessary to use multiple metallization layers to connect the various semiconductor devices together to form a circuit. The metallization layer includes contact vias and interconnects and utilizes the contact vias and interconnects as electri...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311H01L21/768
Inventor 隋运奇王新鹏
Owner SEMICON MFG INT (SHANGHAI) CORP