Single-chip package manufactured by using tin-silver-copper alloy immersion method and manufacturing process of single-chip package

Abstract

The invention discloses a single-chip package manufactured by using a tin-silver-copper alloy immersion method and a manufacturing process of the single-chip package. The package mainly comprises a frame inner lead, tin layers, metal bumps, a chip and a plastic package body, wherein the metal bumps are formed from the surface of a pressing region of the chip by using a tin-silver-copper alloy immersion method; an electroplated tin layer is arranged at a welding region of the frame inner lead and each metal bump; the tin layers are arranged on the frame inner lead; the metal bumps are arranged on the tin layers; the chip is arranged on the metal bumps; the frame inner lead, the tin layers, the metal bumps and the chip are enclosed by the plastic package body; and a power and signal channel of a circuit is formed by the chip, the metal bumps, the tin layers and the frame inner lead. The manufacturing process is performed according to the following steps of: immersing a wafer in tin-silver-copper alloy to form the high-temperature solder ball metal bumps; thinning and scribing the wafer; plating the tin layers on corresponding regions of a frame; loading the chip; performing reflow welding; performing plastic packaging; post-curing; tinning; printing; separating a product; checking; and packaging. The manufacturing process has the characteristics of low cost and high efficiency.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit packaging, and in particular relates to a single-chip package made by immersion-tin-silver-copper alloy method and a manufacturing process thereof. Background technique [0002] With the rapid development of microelectronics technology and the increase in the complexity of integrated circuits, most of the functions of an electronic system may be integrated in a single chip (system on chip), which requires microelectronic packages to have higher performance and more More leads, denser interconnection, smaller size or larger chip cavity, greater heat dissipation function, better electrical performance, higher reliability, lower cost per lead, etc. The chip packaging process has changed from chip-by-chip packaging to wafer-level packaging. Wafer-level chip packaging technology——WLCSP just meets these requirements and forms a compelling WLCSP process. [0003] Wafer Level Chip Scale Packa...

AI Technical Summary

Problems solved by technology

Not conducive to the realization of product mass production

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