Novel silicon substrate low resistance inductance structure and wafer level encapsulating method thereof

Abstract

The invention relates to a novel silicon substrate low resistance inductance structure and a wafer level encapsulating method of the novel silicon substrate low resistance inductance structure, and belongs to the technical field of semiconductor encapsulation. A coil groove (102) is formed in the upper surface of a silicon wafer (100) in an etching mode, an insulation layer (300) is coated inside the coil groove (102), an electroplating seed layer (300) is arranged in a deposit mode through a physical method, a thick copper metal wiring layer (400), namely an inductance coil, is formed in the coil groove (102) in a photoetching imaging mode through an electroplating technology, and finally, a secondary passivating layer (500) and metal leading wires (600) are arranged on the thick copper metal wiring layer (400), and the thick copper metal wiring layer (400) is communicated with the thick copper metal wiring layer (400) through an secondary passivating layer opening (501). According to the novel silicon substrate low resistance inductance structure and a wafer level encapsulating method of the novel silicon substrate low resistance inductance structure, the copper metal wiring layer serving as the inductance coil is embedded into the interior of a silicon substrate body, technological difficulty and technological cost of preparation of the inductance coil are reduced, an encapsulating density is improved, meanwhile direct current resistance of an inductor is reduced by increasing the thickness of coils, and a quality factor of the inductor is improved.

Description

technical field [0001] The invention relates to a novel silicon-based low-resistance inductance structure and a wafer-level packaging method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] With the development of packaging technology, system-in-package (SIP, system in package) is becoming more and more popular due to its better electrical performance and smaller package size. In the packaging field of power management devices such as DC-DC converters, people try to integrate discrete inductors and power management chips into a system-in-package, but the current ceramic-based discrete inductors are large in size and cannot meet the requirements of miniaturization of the package. Silicon-based planar spiral inductors are an alternative to discrete inductors due to their small size and high precision. [0003] At present, the wiring process on the silicon substrate used to make silicon-based spiral inductors is mainly a rewir...

AI Technical Summary

Problems solved by technology

The following process problems exist in the thick resist process: after the photoresist is spin-coated, the uniformity of the resist thickness is poor; the photolithography exposure process is difficult to control due to the uneven thickness of the photoresist; Residue

Therefore, using the above process, that is, the rewiring method in which the photoresist forms the wiring pattern, and the wiring layer is arranged on the surface of the silicon base body, the requirements for the photoresist material are high, the process is difficult, the process cost is high, and the packaging density is also limited. promotion

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