A three-dimensional interconnect structure and its preparation method

A three-dimensional interconnection and metal wiring layer technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problems of high-speed and high-frequency transmission performance, and achieve small signal reflection and medium Less loss, good high-frequency performance

Active Publication Date: 2016-09-21
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In order to solve the above-mentioned technical problems of poor high-speed and high-frequency transmission performance, the present invention provides a new three-dimensional interconnection structure and its preparation method

Method used

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  • A three-dimensional interconnect structure and its preparation method
  • A three-dimensional interconnect structure and its preparation method
  • A three-dimensional interconnect structure and its preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0069] combine Figure 2 to Figure 3 (11) The manufacturing method of the first embodiment is described in detail. The preparation method of the three-dimensional interconnection structure described in the first embodiment includes the preparation of a front metal wiring layer and a back metal wiring layer. figure 2 is a schematic flow chart of the manufacturing method of this embodiment, Figure 3(1) to Figure 3(11) It is a structural diagram corresponding to a series of manufacturing processes of the manufacturing method of this embodiment.

[0070] see figure 2 , the production method includes the following steps:

[0071] S201, forming trapezoidal grooves on the front surface of the semiconductor substrate;

[0072] In the semiconductor manufacturing process, the etching region formed by selective etching or anisotropic etching is generally a groove with a wide top and a narrow bottom, generally a trapezoidal groove. The selective etching is generally dry etching, s...

Embodiment 2

[0108] The method for preparing the three-dimensional interconnection structure described in the second embodiment includes preparing two layers of front metal wiring layers and two layers of back metal wiring layers. It can be understood that those skilled in the art can also obtain three or more front metal wiring layers and back metal wiring layers according to the method of preparing two front metal wiring layers and two back metal wiring layers. Embodiment 1 has many similarities with Embodiment 2. For the sake of brevity, this embodiment only focuses on the differences. For the similarities, please refer to the description of Embodiment 1.

[0109] combine Figure 4 to Figure 5 (14) The preparation method of this example is described. The preparation method of the three-dimensional interconnection structure comprises the following steps:

[0110] Steps S401 to S403 are the same as steps S201 to S203 in the first embodiment, and for the sake of brevity, no detailed desc...

Embodiment 3

[0168] see Figure 3 (11) , the three-dimensional interconnection structure includes,

[0169] A semiconductor substrate 100, the semiconductor substrate 100 includes opposite front and back, the semiconductor substrate is formed with a trapezoidal hole 101 through the front and back, the opening of the trapezoidal hole on the front of the semiconductor substrate 100 is larger than an opening on the back side of the semiconductor substrate 100;

[0170] It should be noted that the trapezoidal grooves are formed on the front side of the semiconductor substrate by selective etching, and after the front side process is completed, the thickness of the semiconductor substrate 100 is ground and thinned to form a trapezoidal hole structure.

[0171] The front insulating layer 102 located above the front of the semiconductor substrate 100 and above the slope of the trapezoidal hole 101; since there is no front insulating layer 102 at the bottom of the trapezoidal hole 101, the front ...

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Abstract

The invention provides a three-dimensional interconnection structure and a preparation method thereof. A trapezoidal groove is formed on the front surface of a semiconductor substrate, and then at least one front metal wiring layer is arranged on the slope of the trapezoidal groove, and then the back surface of the semiconductor is ground to make the Each layer of the front metal wiring layer near the bottom of the trapezoidal groove on the slope of the trapezoidal groove is exposed, and then at least one back metal wiring layer is formed on the back of the semiconductor and under the exposed front metal wiring layer. The metal wiring layer on the front side of the semiconductor and the metal wiring layer on the back side of the semiconductor are electrically connected through the metal wiring layer on the trapezoidal groove. In the three-dimensional interconnection structure provided by the present invention, the front metal wiring layer located on the slope of the trapezoidal groove is equivalent to a transmission belt, which can realize the formation of interconnection lines with the same or similar impedance between the front surface of the semiconductor, the slope of the trapezoidal groove, and the back surface of the semiconductor. It can overcome the problem of large signal reflection caused by impedance mismatch.

Description

technical field [0001] The invention relates to the field of electronic packaging, in particular to a three-dimensional interconnection structure and a preparation method thereof. Background technique [0002] As the feature size of integrated circuits continues to shrink, chip complexity continues to increase and interconnect densities continue to increase. Due to the low interconnect density, wire bonding can no longer meet the requirements of multi-chip high-density packaging. In order to meet the high interconnection density, shorten the interconnection path, and solve the interconnection bottleneck of three-dimensional stacking, a new packaging technology, that is, three-dimensional integrated circuit (3D-IC) technology using Through-Silicon-Via (TSV) Came into being. [0003] 3D-TSV integration technology is one of the core technologies of microelectronics. 3D-TSV interconnection provides a method beyond "Moore". It is currently the most advanced and complex packagin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/532H01L23/528H01L21/768
CPCH01L2224/13
Inventor 李君曹立强戴风伟
Owner NAT CENT FOR ADVANCED PACKAGING
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