Production method of semiconductor device

Abstract

The invention discloses a production method of a semiconductor device. The production method includes: forming a gate stack structure on a substrate; etching parts of the substrate, on two sides of the gate stack structure, to form C-shaped source-drain trenches; wet-etching the C-shaped source-drain trenches to form sigma-shaped source-drain trenches. According to the production method of the semiconductor device, the C-shaped source-drain trenches are etched and sigma-shaped source-drain trenches are formed by further wet etching; accordingly, channel area stress is increased effectively, the depth of source-drain trenches is controlled precisely, defects are reduced, the sidewall and bottom of each trench is less rough, and the performance of the device is improved.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, and more specifically, to a semiconductor device method with Σ-type source and drain. Background technique [0002] After entering the 90nm node, strained silicon technology has become a basic technology to improve the performance of MOSFET devices by suppressing the short channel effect and improving carrier mobility. In the strained silicon technology, stress technologies such as STI, SPT, source-drain silicon germanium embedding, metal gate stress, etch stop layer (CESL) have been proposed successively, and various schemes are used to apply stress to the channel region to increase the current carrying capacity. sub-mobility to improve actuation. [0003] Among these technologies, the source-drain silicon-germanium embedded technology is gradually adopted by mainstream CMOS process manufacturers after entering the 90nm node. The method of epitaxially growing silic...

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Problems solved by technology

[0007] However, in the above existing processes, due to the relatively large distance a1, the SiGe and / or SiC stress source and drain regions have to go through a long distance to apply stress to the channel region, and the actual increase in stress obtained by the channel region is limited.

In addition, if a1 is increased unilaterally, it means that during the process of wet etching groove 1B to form groove 1C, either the etching rate is increased or the etching time is prolonged, which will cause the distance b1 to increase unnecessarily and increase the Defects at the bottom of groove 1C, reducing the quality of epitaxial SiGe and / or SiC

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