Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor structure using plasma to control feature size and manufacturing method thereof

A feature size, plasma technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as costing a lot of time and money, and achieve the effect of saving time and money

Active Publication Date: 2016-09-07
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Although, in the prior art, it is possible to adjust the above-mentioned ACT feature size (i.e., the distance X1 or X1’) by designing a new mask, or by using the optical proximity correction method (OPC), but this often takes a lot of time and money

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor structure using plasma to control feature size and manufacturing method thereof
  • Semiconductor structure using plasma to control feature size and manufacturing method thereof
  • Semiconductor structure using plasma to control feature size and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] Such as Figure 4 Shown is the semiconductor structure using plasma to control the feature size of the present invention, which is a schematic diagram of a logic device 100 during shallow trench isolation (STI) process. The semiconductor structure includes a silicon Si substrate 10; a pad oxide layer 20 (Pad Oxide) is formed on the substrate 10; a hard mask of silicon nitride SiN is formed on the pad oxide layer 20 layer 30; a bottom anti-reflection layer 40 (BARC) is covered on the hard mask layer 30; and a photoresist 50 (PR) is covered on the bottom anti-reflection layer 40, and through a photolithography process, according to the design A good pattern is formed as a photo mask.

[0045] By plasma dry etching method, the bottom anti-reflection layer 40 and the hard mask layer 30 are etched downward to form the first trench 61 at the position not covered with the photoresist 50 on the bottom anti-reflection layer 40, so that the substrate The pad oxide layer 20 is e...

Embodiment 2

[0059] Such as Image 6 What is shown is a schematic diagram of the semiconductor structure of the present invention being a flash memory device 200 in another embodiment when a shallow trench isolation (STI) process is performed. Most of the semiconductor structure is similar to the structure shown in the logic device 100, except that the pad oxide layer 20 ( Figure 4 ) is replaced by first forming a coupling oxide layer 21 (coupling oxide), and then forming a polysilicon film 22 (ie, FG POLY floating gate polysilicon film) on the coupling oxide layer 21 . Similar to the above, the hard mask layer 30, the bottom anti-reflection layer 40, and the photoresist 50 as a photomask are successively formed, and, after using a mixed gas such as carbon tetrafluoride CF4 and hydrogen bromide HBr In the process of forming the first trench 61 by etching with plasma, a passivation layer 70 is formed at the sidewall position of the first trench 61, so that the photoresist 50, the bottom a...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a semiconductor structure using plasma to control the feature size and a manufacturing method thereof. During the shallow trench isolation process, by adjusting the plasma used for etching the first trench, the first trench can be etched. A passivation layer is formed on the sidewall. Therefore, when the width of the hard mask layer is constant after etching, the increase in the thickness of the passivation layer on both sides of the hard mask layer is used to adjust the ACT feature size; The width distance of the second trench formed by etching (ie, the ADI feature size) is adjusted so that the finished semiconductor structure meets the relevant requirements of the wafer electrical test (WAT). In the present invention, it is not necessary to design a new photomask and use an optical proximity correction method (OPC) to realize the adjustment of the ACT feature size, which saves a lot of time and money.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure using plasma to control feature size and a manufacturing method thereof. Background technique [0002] like figure 1 The semiconductor structure shown is the structure of the logic device 100 during shallow trench isolation (STI) process, which includes a silicon Si substrate 10; a pad oxide layer is formed on the substrate 10 20 (Pad Oxide); a hard mask layer 30 of silicon nitride SiN is formed on the pad oxide layer 20; a bottom anti-reflection layer 40 (BARC) is covered on the hard mask layer 30; and in the The bottom anti-reflection layer 40 is covered with a photoresist 50 (PR), and is formed into a photomask (Photo Mask) according to a designed pattern. [0003] By using, for example, plasma of carbon tetrafluoride gas CF4 to perform dry etching, the bottom anti-reflective layer 40 and the hard mask layer 30 are etched downward at the position where...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/8247
CPCH01L21/76224H10B69/00
Inventor 程江伟许昕睿
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP