Method for restraining reverse narrow channel effect in shallow trench isolation technology

Abstract

The invention discloses a method for restraining the reverse narrow channel effect in the shallow trench isolation technology. The method comprises the steps that a first silicon dioxide layer and a second silicon nitride layer are sequentially formed; an active area is defined and a hard mask layer outside the active area is removed; a shallow trench is etched; a third oxide layer is formed on the surface of the shallow trench; the second silicon nitride layer is etched according to the wet etching technology, so that the edge area of the active area is exposed; ion injection is conducted at an inclined angle, ions are injected into the edge area of the active area; a oxide layer of the shallow trench is filled; chemical mechanical grinding is conducted on the oxide layer of the shallow trench. According to the method for restraining the reverse narrow channel effect in the shallow trench isolation technology, after the edge area of the active area is exposed, ion injection is conducted at the inclined angle, so that the doping concentration of the active area is improved, the threshold voltage of a metal oxide semiconductor device on the edge area of the active area is increased, the frequency of electric leakage of the device on the edge area of the active area is reduced, the performance uniformity of the device is improved, and the reverse narrow channel effect in the shallow trench isolation technology is effectively restrained.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a method for suppressing reverse narrow channel effect in shallow trench isolation process. Background technique [0002] In the metal oxide semiconductor process using shallow trench isolation, the existing shallow trench isolation process includes the following steps: [0003] A sacrificial oxide layer and silicon nitride are sequentially formed on the surface of the silicon substrate; a hard mask layer is composed of the sacrificial oxide layer and silicon nitride. [0004] The active area is defined by a photolithography process. [0005] The hard mask layer outside the active region is removed by an etching process. [0006] Shallow trench etching is performed to form shallow trenches in the silicon substrate formed outside the active region. [0007] Shallow trench oxidation is performed to form an oxide layer on the bottom surface and si...

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Problems solved by technology

Especially under the condition of increasing substrate bias voltage (Vb), the leakage increases more

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