SiC epitaxial wafer and method for manufacturing same

A technology for epitaxial wafers and manufacturing methods, which is applied in chemical instruments and methods, semiconductor/solid-state device manufacturing, crystal growth, etc., and can solve problems such as the expansion of lamination defect areas

Active Publication Date: 2014-04-30
SHOWA DENKO KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Furthermore, in a bipolar device such as a pn diode, one of the above two incomplete dislocations has Si as a crystal nucleus, and the other has C as a crystal nucleus, and only the

Method used

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  • SiC epitaxial wafer and method for manufacturing same
  • SiC epitaxial wafer and method for manufacturing same
  • SiC epitaxial wafer and method for manufacturing same

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Example

[0063] (First Embodiment)

[0064] The method of manufacturing a SiC epitaxial wafer according to the first embodiment of the present invention is a method of manufacturing a SiC epitaxial wafer having an SiC epitaxial layer on a SiC single crystal substrate having an off angle, and is characterized in that it includes: determining the off angle The process of the ratio of the SiC epitaxial film formed on the SiC single crystal substrate with a predetermined film thickness among the basal plane dislocations (BPD) existing on the growth surface of the SiC single crystal substrate as a lamination defect; determine based on the ratio The process of using the upper limit of the BPD areal density on the growth surface of the SiC single crystal substrate used; and using the SiC single crystal substrate below the upper limit under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio, in the SiC single crystal substrate The process ...

Example

[0126] (Second Embodiment)

[0127] The method for manufacturing a SiC epitaxial wafer according to the second embodiment of the present invention is a method for manufacturing a SiC epitaxial wafer having an SiC epitaxial layer on a SiC single crystal substrate having an off angle, and is characterized in that it has: Among the basal plane dislocations (BPD) and threading screw dislocations (TSD) existing on the growth surface of the SiC single crystal substrate, the ratio of carrot defects in the SiC epitaxial film of a predetermined thickness formed on the SiC single crystal substrate Process; the process of determining the upper limit of the areal density of the BPD on the growth surface of the SiC single crystal substrate used based on the ratio; and using the SiC single crystal substrate below the upper limit so that the growth conditions of the epitaxial film used in the process of determining the ratio are the same Conditions, the process of forming a SiC epitaxial film o...

Example

[0147] (Example 1)

[0148] A SiC epitaxial wafer with a SiC epitaxial layer formed on the Si surface of a 4H-SiC single crystal substrate inclined at an off angle of 4° was manufactured.

[0149] In this embodiment, the 4H-SiC single crystal substrate is not subjected to convex processing.

[0150] First, in order to determine the conversion efficiency to build-up defects (SF), four SiC single crystal substrates were polished under four polishing conditions. The areal densities of the four basal plane dislocations (BPD) shown in Table 1 are equivalent to the areal density of basal plane dislocations (BPD) of the SiC single crystal substrate polished under these polishing conditions.

[0151] In addition, the one with the lowest BPD density was performed under the following polishing conditions. That is, the mechanical polishing before CMP uses abrasive grains with a diameter of 5 μm or less, and the processing pressure is 350 g / cm 2 To proceed. In addition, CMP was performed using ...

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Abstract

The present invention relates to a SiC epitaxial wafer with a reduced surface density of a stacking fault, and a method for manufacturing the same. The method of the present invention comprises determining a stacking fault ratio at a SiC epitaxial membrane having a predetermined thickness formed on a SiC single crystal substrate in a basal plane dislocation (BPD) present at a growth plane of the SiC single crystal substrate having an off angle, determining an upper limit of a surface density of the BPD at the growth plane of the SiC single crystal substrate in use based on the ratio, and forming the SiC epitaxial membrane on the SiC single crystal substrate by using the SiC single crystal substrate below the upper limit in the same condition as a growth condition of the epitaxial membrane used when determining the ratio.

Description

technical field [0001] The invention relates to a SiC epitaxial wafer and a manufacturing method thereof. [0002] This application claims priority based on Patent Application No. 2011-197626 for which it applied to Japan on September 9, 2011, The content is used for this application. Background technique [0003] Silicon carbide (SiC) has excellent characteristics such as about 10 times larger dielectric breakdown electric field and about 3 times larger band gap than silicon (Si), so it is expected to be applied to power devices, high-temperature operating devices, and the like. [0004] The SiC device is generally produced using a SiC epitaxial wafer, which is obtained by processing a SiC single crystal substrate obtained by processing a bulk single crystal of SiC grown by a sublimation recrystallization method, etc., by chemical vapor growth (Chemical Vapor Deposition) : CVD) etc. to grow the SiC epitaxial film that becomes the active region of the device. [0005] It i...

Claims

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Application Information

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IPC IPC(8): H01L21/205C23C16/42C30B25/20C30B29/36
CPCH01L21/02617H01L21/02433C30B29/36H01L21/02529C30B25/20H01L21/02378H01L21/02658H01L21/0262H01L29/045H01L21/02634C30B25/186H01L21/02024H01L29/32H01L29/1608H01L21/02046
Inventor 百濑贤治小田原道哉武藤大祐影岛庆明
Owner SHOWA DENKO KK
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