A kind of manufacturing method of semiconductor device based on double pattern

Abstract

The invention relates to a semiconductor device manufacturing method based on double patterning. The method comprises the following steps: a semiconductor substrate and a mask layer located on the substrate are provided; a patterned photoresist layer is formed on the mask layer, wherein the patterned photoresist layer is photoresist cores separated through openings; a crosslinked top surface layer is formed on the patterned photoresist layer; a part of the photoresist layer sidewall is removed to thin the photoresist cores and reduce the critical size of the photoresist cores; spin coating is performed on the inner sidewall material layer, and the crosslinked top surface layer is covered; the etch back operation is performed on the inner sidewall material layer to form inner sidewalls on the photoresist cores; and the remaining crosslinked top surface layer and remaining photoresist cores are removed to form a double-patterned mask. The method of the invention is more simple, the stress problem caused by inner sidewall material chemical vapor deposition does not exist, and etch steps are reduced, so the cost is greatly reduced, and the product yield can be further improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and in particular, the invention relates to a method for manufacturing a semiconductor device based on a double pattern. Background technique [0002] The demand for high-capacity semiconductor storage devices is increasing day by day, and the integration density of these semiconductor storage devices has attracted people's attention. In order to increase the integration density of semiconductor storage devices, many different methods have been adopted in the prior art, such as by reducing the wafer size. And / or change the internal structure unit, and form a plurality of memory units on a single wafer, for the method of increasing the integration density by changing the unit structure, attempts have been made to reduce the Small unit area. [0003] Double-Patterning (DP) overcomes the K1 limitation through pitch fragmentation, and thus is widely used in the preparation of semiconductor...

AI Technical Summary

Problems solved by technology

In order to reduce costs, the second method can be selected, such as image 3 As shown in A, a photoresist pattern is directly formed on the substrate, and then a spacer material layer is deposited on the photoresist pattern, but because the hardness of the photoresist is not enough, it is not enough to bear the spacer The pressure of the material layer and the pressure during etching, so it is easy to deform the pattern on the photoresist, resulting in Figure 4 The pattern of B, the device is severely deformed when performing double patterning technology, such as Figure 5 B, and the process is also unavoidable to perform the CVD process

[0005] Therefore, although there is a double-patterning technology in the prior art, there are problems of cumbersome process and high cost. If the cost is reduced, the quality of the product cannot be guaranteed, causing serious deformation of the device, resulting in a reduction in the product qualification rate. Therefore, it is necessary to Improve the above method to eliminate the existing problems

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