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Groove of P type LDMOS device and manufacture method of groove

A manufacturing method and trench technology, which are applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of difficult control of N-type polysilicon etching and difficult process, so as to prevent short channel effect and high Performance, the effect of good electrical connection

Active Publication Date: 2014-06-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the formation of polysilicon deep trenches 3, the etching of highly doped N-type polysilicon is relatively difficult to control. In the traditional process, the reserved depth of N-type polysilicon is guaranteed by timing etching and equipment control. very difficult

Method used

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  • Groove of P type LDMOS device and manufacture method of groove
  • Groove of P type LDMOS device and manufacture method of groove
  • Groove of P type LDMOS device and manufacture method of groove

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Embodiment Construction

[0033] The trench of the P-type LDMOS device according to the present invention has a structure such as Figure 11 As shown, the P-type LDMOS is located in the epitaxy 2 on the substrate 1, has a lightly doped drain region 8 and an N-type channel region 5 that are in contact with each other, and the source region 10 of the P-type LDMOS is located in the N-type In the channel region 5, the drain region 9 is located in the lightly doped drain region 8, and the surface of the epitaxy 2 has the gate oxide 6 and the polysilicon gate 7 of the P-type LDMOS device, and the polysilicon gate 7 is covered with tungsten silicon 13; The trench 17 of the P-type LDMOS device is located in the source region 10 and is divided into upper and lower ends. The width of the upward trench 17 gradually increases to form a slope, which is funnel-shaped. The lower end of the trench 17 is filled with heavily doped N-type polysilicon 18 , and the upper end is filled with metal silicide 12 .

[0034] The...

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Abstract

The invention discloses a groove of a P type LDMOS device. In a P type LDMOS device, a source is required to be electrically connected with a substrate, a polycrystalline silicon deep trench is traditionally adopted, as a result, problems of complex techniques and proneness to formation of electric leakage may be brought about. According to the groove of the P type LDMOS device, a surface channel is formed in a source region so as to connect the source region with the substrate. The invention also discloses a manufacture method of the groove of the P type LDMOS device. According to the manufacture method of the groove of the P type LDMOS device, the source region is opened through wet etching, and the groove is manufactured in the source region, and at the same time, a smooth inner oblique surface of the groove of the source region can be formed through utilizing the isotropy of dry etching, and then, a metal silicide is manufactured subsequently. The groove of the P type LDMOS device and the manufacture method of the groove of the invention are advantages in improved electrical connection between the source region and the substrate, easiness in height limitation, simplicity and easiness in implementation.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a trench of a P-type LDMOS device, and also relates to a manufacturing process for the trench. Background technique [0002] The electronic components of battery-powered portable electronic products are required to have smaller volume and lower leakage, and the devices also need to have fast switching speed. P-type power MOSFETs, formed by arrays of gates to obtain an output current greater than 10 amperes, are widely used in power management circuits of portable electronic products. A large array means that the total gate width is large, and how to achieve good uniformity to maintain low leakage is a big challenge. At the same time, in order to obtain high switching speed, the threshold voltage of MOSFET should be lower, but the low threshold voltage will cause higher leakage current. Compared with buried trenches, surface trench devices offer a compromise of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L29/0638
Inventor 马彪遇寒蔡莹
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP