Forming method for transistor

Abstract

The invention discloses a forming method for a transistor. The forming method comprises the following steps of providing a semiconductor substrate, and forming a pseudo gate, and a source area and a drain area, which are positioned in the semiconductor substrate on the two sides of the pseudo gate, on the semiconductor substrate; forming an interlayer dielectric layer on the semiconductor substrate to cover the source area and the drain area; after the interlayer dielectric layer is formed, removing the pseudo gate to form a pseudo gate trench in a dry etching way; after the pseudo gate is removed in the dry etching way, removing a polymer generated in a dry etching process in a wet corrosion way, wherein the PH value of a corrosive agent is greater than 6 and smaller than 7 or greater than 7 and smaller than 8, and the corrosive agent contains fluoride; after the polymer is removed in the wet corrosion way, forming a gate in the pseudo gate trench. According to the forming method, the corrosive agent is used for substantially removing the polymer on the sidewalls and the bottom of the pseudo gate trench, and the gate can form barrier-free contact with the dielectric layer of the gate or the gate on the sidewalls of the pseudo gate trench; the performance of the transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a transistor. Background technique [0002] In the prior art, a "gate last" process is a main process for forming a metal gate. The characteristic of this technology is that the metal gate is formed after the drain / source region ion implantation operation and the subsequent high temperature annealing step are completed on the silicon wafer. [0003] In the gate-last process of the prior art, the method for forming a transistor generally includes: first, forming a dummy gate on a semiconductor substrate; then, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate; Next, an interlayer dielectric layer is formed on the semiconductor substrate to cover the source region and the drain region, and the upper surface of the interlayer dielectric layer is flat with the upper surface of the dummy gate; next, t...

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Problems solved by technology

[0006] The problem solved by the present invention is that the performance o

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