Method for manufacturing double-layer polysilicon bipolar transistor

Abstract

The invention discloses a method for preparing a high-performance double-layer polysilicon bipolar transistor, which includes the following steps: 1) using LOCOS and CVD to deposit SiO2 to form a composite isolation structure to reduce high-temperature process time; 2) using SiO2 as the base The etch stop layer of extremely polysilicon prevents etching damage; 3) SiO2 and N+ polysilicon are used to form a composite sidewall structure to reduce emitter resistance. Advantages: Reduce the high-temperature process time without reducing the isolation effect, so that a relatively thin epitaxial layer can be used to obtain better microwave performance, and silicon dioxide is used as the etch stop layer to eliminate the etching of the silicon epitaxial layer Corrosion damage, improve breakdown characteristics, increase current amplification factor, reduce noise figure. The silicon dioxide and N+ polysilicon composite sidewall structure can reduce the emitter resistance while ensuring the electrical isolation of the emitter-base, increase the current amplification factor, and reduce the noise figure.

Description

technical field [0001] The invention relates to a method for manufacturing a high-performance double-layer polysilicon bipolar transistor, which belongs to the technical field of microelectronic design and manufacture. Background technique [0002] At present, in the field of wired and wireless communication, compound semiconductor devices, such as GaAs HBT or HEMT, SiGe HBT, etc., have high cut-off frequency and low noise figure due to their inherent material characteristics, and are used in low-noise amplifiers and mixers. It has been widely used in circuits such as. Silicon-based devices, due to lower mobility, their high-frequency performance is inferior to the above-mentioned devices, but at the low end of the microwave, in small and medium power amplifiers and mixer applications in RF front-end and baseband circuits, compared with compound low-noise devices , The advantages of silicon-based BJT are low phase noise, mature technology, and low cost, so it has strong mar...

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Problems solved by technology

The advantage of the dielectric side wall structure is that the isolation effect is good, and the disadvantage is that the current conduction area of ​​the emitter is reduced, that is, the emitter resistance is increased.

The reason is that for a high-performance double-layer polysilicon BJT, the P+ polysilicon spacing is generally 0.6 μm to 1.0 μm (not too large, too large will increase the base-emitter distance, increase the lateral size of the device, and increase the parasitic resistance of the base) , the width of the sidewall is generally 0.1 μm to 0.3 μm, and the width of the emission area is generally 0.3 μm to 0.6 μm. Such a small width of the emission area introduces a larger emitter resistance, thereby reducing the current amplification factor and increasing the noise figure.

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