Method for forming a semiconductor device containing a strained silicon layer

Abstract

The invention discloses a method for forming a semiconductor device comprising a strain silicon layer. In the method, a hard mask layer is utilized for simultaneously defining the position of a strain silicon layer which has tensile stress applied thereto in the area of an NMOS transistor and the position of a strain silicon layer which has crushing stress applied thereto in the area of a PMOS transistor so that the relative position of the strain silicon layer which has the tensile stress applied thereto in the area of the NMOS transistor and the strain silicon layer which has the crushing stress applied thereto in the area of the PMOS transistor satisfies a demand, thus the yield and the product performance of the semiconductor device with the strain silicon layer are improved.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device containing a strained silicon layer. Background technique [0002] In the past thirty years, the integrated circuit industry has been developing in accordance with the guidance of Moore's Law. Since 2001, according to ITRS prediction, the feature size of MOSFET (Metal Oxide Field Effect Transistor) has shrunk by 70% every three years, and at the same time, the integration level of circuits has quadrupled. When the feature size of MOSFET is reduced, on the one hand, in order to suppress the short channel effect and prevent the source-drain through, the doping concentration in the channel must increase; on the other hand, in order to maintain a good driving current and improve the short channel effect , the thickness of the gate oxide film must be thinned, but the threshold voltage and power supply voltage cannot be scaled down...

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Problems solved by technology

[0014] It can be seen that, in the step of patterning the first hard mask layer 4, it is necessary to register the pattern on the mask plate and the existing pattern on the semiconductor device once, and then to the second hard mask layer 5 and In the step of patterning the first hard mask layer 4, it is necessary to register the pattern on the mask plate with the existing pattern on the semiconductor device, so that the opening formed in the second hard mask layer 5 can be easily The relative position between the openings formed in the first hard mask layer 4 does not meet the registration accuracy requirements, so that the strained silicon layer 7A to which tensile stress is applied in the NMOS transistor region 1A and the strained silicon layer 7A to which compressive stress is applied to the PMOS transistor region 1B The relative position between the strained silicon layers 7B does not meet the requirements, thereby reducing the yield and product performance of semiconductor devices containing strained silicon layers

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