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Network on chip with network coding function, network topology of the network on chip, and route algorithm of the network topology

A network coding and network-on-chip technology, applied in the field of network-on-chip and its network topology and routing algorithms, can solve problems such as reducing network throughput and failing to achieve maximum transmission capacity, and achieves improved network throughput, improved bandwidth utilization, and improved The effect of overall performance

Inactive Publication Date: 2014-10-08
XIDIAN UNIV +1
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Problems solved by technology

[0004] Many kinds of multicast packets may arrive at an intermediate router at the same time. Since ordinary routing nodes can only forward one kind of multicast packets at a time, other multicast packets need to wait in line, which reduces the throughput of the network, and cannot be achieved by the "maximum flow rate". The maximum transmission capacity determined by the minimum cut theorem

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  • Network on chip with network coding function, network topology of the network on chip, and route algorithm of the network topology
  • Network on chip with network coding function, network topology of the network on chip, and route algorithm of the network topology
  • Network on chip with network coding function, network topology of the network on chip, and route algorithm of the network topology

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Embodiment Construction

[0018] The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0019] This example provides an on-chip network with encoding function, including an upper sub-router and a lower sub-router. The upper sub-router is used to process packet data transmitted upward in the network, and the lower sub-router is used to process packet data transmitted downward in the network; this example The upper sub-router includes an input module, a network coding module, a switch distribution module, a crossbar switch module and an output module; the output terminals of the switch distribution module and the crossbar switch module are respectively connected to the output module signal, and the input terminal of the network coding module is connected to the input module. The output terminal is signal connected, and the output terminal of the network coding module is respectively connected with the input terminal of ...

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Abstract

The invention discloses a network on chip router with a network coding function, a network topology applied to the network on chip, and a route algorithm of the network topology. A coding sub-module codes received multiple packet data, the coded data is forwarded in a multicast mode from an intermediate route node, and a decoding sub-module, according to known information, decodes the received data to restore the received data to original data. A network coding module realizes compression of the packet data, so that information content carried by data transmitted through a network is increased, the problem of how to reach a network transmission capacity limit is solved, network scale expansion is facilitated, and the network coding function can reduce the network load and improve the network performance.

Description

technical field [0001] This application relates to the field of communication technology, in particular to an on-chip network with network coding function and its network topology and routing algorithm used in the field of scientific research. Background technique [0002] With the development of integrated circuit technology, the shortcomings of bus-structured system-on-chip are becoming more and more prominent. In order to overcome these shortcomings, network-on-chip (NoC) came into being. The network on chip adopts a reasonable topology structure and introduces routing and switching theory, so its parallel communication characteristics can meet the needs of future development. For example, in 2012, Intel's latest on-chip network processor Xeon Phi 5110P integrated 60 IP cores with 22nm process 3D transistors, operating frequency up to 1.053GHz, and achieved double-precision peak performance up to 1.011TFlops, becoming a high-performance computing platform. new foundation...

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Application Information

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IPC IPC(8): H04L12/761H04L29/06H04L12/801G06F15/78H04L45/16
Inventor 付希松顾华玺朱键王铮杨银堂
Owner XIDIAN UNIV
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