Preparation method of flash memory

Abstract

The invention provides a preparation method of a flash memory. The invention adopts a method of combining dry etching in the middle of twice wet etching to form a trench located at an isolation structure between floating gates. Compared with the pure wet etching in the prior art, the present invention forms a silicon oxide barrier layer to protect the floating gate before the increased dry etching, therefore, when performing the dry etching of the anisotropic etching, the In the case of ensuring that the width of the floating gate is not damaged, a groove with an inverted trapezoidal cross-section is formed to increase the shortest distance between the active region and the control gate while ensuring the consistency of the distance, which is conducive to increasing the control gate of the flash memory. The capacitive area between the floating gate and the floating gate increases the gate coupling coefficient, thereby increasing the rated leakage current of the memory, thereby improving the erasing speed of the flash memory and the reliability of the device during cycle operation; both the isolation structure and the silicon oxide barrier layer are oxidized For silicon, only the same solution needs to be used for etching after dry etching, saving process steps and reducing costs.

Description

technical field [0001] The invention belongs to the manufacturing field of semiconductor devices, and relates to a preparation method of a flash memory. Background technique [0002] Flash memory (Flash Memory, referred to as flash memory) is a fast-growing non-volatile semiconductor memory. It not only has the advantages of fast reading speed and large storage capacity of semiconductor memory, but also overcomes the loss of power when the power is cut off like DRAM and SRAM. Defects in stored data. It can be rewritten like EPROM and EEPROM, and it is easier to rewrite than them and the price is relatively cheap. Since it was first introduced by Intel in 1988, flash memory has been used in thousands of products, including mobile devices such as mobile phones, laptops, PDAs and USB flash drives, as well as devices such as network routers and cabin recorders. in industrial products. Compared with computer hard disks, it not only has fast access, but also is small in size, l...

AI Technical Summary

Problems solved by technology

[0006] Due to the limitations of the existing planarization process, such as the limitation of control precision in the chemical mechanical polishing process (CMP), the consistency of the floating gate height in the preparation of flash memory is reduced, and due to the isotropic characteristics of wet etching, The depth of the groove formed by pure wet etching of the shallow trench isolation structure between floating gates in the prior art is consistent, so that the channel corner of the active region of each storage unit in the flash memory reaches the bottom of the groove (also That is, the shortest distance L of the control grid) (such as figure 1 As shown) are not consistent, causing a large number of holes to gather at the corners of the channel to generate an edge coupling effect (edge ​​coupling effect) to form a high electric field, and because from a design point of view, the cell drain current margin becomes a limitation Fowler-Nordheim (FN) is an important factor in erasing speed and reducing the memory cell channel feature (degrading cell channel feature), so that a large number of holes accumulated at the channel corners lead to a reduction in the erasing speed of flash memory, therefore, the edge of reducing the erasing speed of flash memory The shortest distance L from the corner of the channel in the active area of ​​each memory cell to the bottom of the groove (that is, the control gate) is not consistent. In addition, the stress-induced interface damage caused by the negative pressure of the control gate in the cycle operation has a negative impact on the channel. The impact caused by the characteristics can even lead to device failure;

[0007] At the same time, the shortest distance L from the corner of the channel in the active region of each memory cell to the bottom of the groove (that is, the control gate) is inconsistent, resulting in a reduction in the capacitance area between the control gate and the floating gate, resulting in a gate coupling coefficient ( gate couplingratio) decreases, when operating the storage unit, it is necessary to apply a larger voltage to be sufficient, the increase in the operating voltage is likely to cause problems such as heat dissipation and noise, and it will also increase power consumption. These situations are critical to the stability and reliability of the memory. very unfavorable

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