A kind of preparation method of flash memory

Abstract

The invention provides a method for preparing a flash memory. The invention adopts a combination of wet etching and dry etching to form a trench located at the isolation structure between floating gates. The cross section of the trench is an inverted trapezoid and the opening has an inverted horn. Compared with the pure wet etching in the prior art, the increased dry etching in the present invention, on the one hand, increases the shortest distance between the active region and the control gate while ensuring the consistency of the distance, which is beneficial to increase the flash memory The capacitive area between the control gate and the floating gate improves the gate coupling coefficient, thereby increasing the rated leakage current of the memory, thereby improving the erasing speed of the flash memory and the reliability of the device during cycle operation; on the other hand, increasing the channel The width of the opening of the groove reduces the aspect ratio of the groove, which is beneficial to improving the density of the material filled in the inverted trapezoidal groove, and at the same time reducing the coupling interference between the floating gates of adjacent memory cells, and improving the reliability of the flash memory.

Description

technical field [0001] The invention belongs to the manufacturing field of semiconductor devices, and relates to a preparation method of a flash memory. Background technique [0002] With the increasing demand for data storage in various mobile devices, there is an increasing demand for non-volatile semiconductor memory (non-volatile memory) that can retain data even when power is turned off. Flash memory (Flash Memory, referred to as flash memory) is a rapidly developing non-volatile semiconductor memory. It not only has the advantages of fast reading speed and large storage capacity of semiconductor memory, but also overcomes the loss of memory when power is cut off like DRAM and SRAM. data flaws. It can be rewritten like EPROM and EEPROM, and it is easier to rewrite than them and the price is relatively cheap. Since it was first introduced by Intel in 1988, flash memory has been used in thousands of products, including mobile devices such as mobile phones, laptops, PDAs...

AI Technical Summary

Problems solved by technology

[0007] 1. Due to the limitations of the existing planarization process, such as the limitation of control precision in the chemical mechanical polishing process (CMP), the consistency of the height of the floating gate in the preparation of flash memory is reduced, and due to the isotropic wet etching The characteristics make the depth of the groove formed by pure wet etching shallow trench isolation structure between floating gates in the prior art consistent, so that the corners of the channel in the active area of ​​each memory cell in the flash memory reach the bottom of the groove (i.e. the control grid) the shortest distance L (such as figure 1 As shown) are not consistent, causing a large number of holes to gather at the corners of the channel to generate an edge coupling effect (edge ​​coupling effect) to form a high electric field, and because from a design point of view, the cell drain current margin becomes a limitation Fowler-Nordheim (FN) is an important factor in erasing speed and reducing the memory cell channel feature (degrading cell channel feature), so that a large number of holes accumulated at the channel corners lead to a reduction in the erasing speed of flash memory, therefore, the edge of reducing the erasing speed of flash memory The shortest distance L from the corner of the channel in the active area of ​​each memory cell to the bottom of the groove (that is, the control gate) is not consistent. In addition, the stress-induced interface damage caused by the negative pressure of the control gate in the cycle operation has a negative impact on the channel. The impact caused by the characteristics can even lead to device failure;

[0008] At the same time, the shortest distance L from the corner of the channel in the active region of each memory cell to the bottom of the groove (that is, the control gate) is inconsistent, resulting in a reduction in the capacitance area between the control gate and the floating gate, resulting in a gate coupling coefficient ( gate couplingratio) decreases, when operating the storage unit, it is necessary to apply a larger voltage to be sufficient, the increase in the operating voltage is likely to cause problems such as heat dissipation and noise, and it will also increase power consumption. These situations are critical to the stability and reliability of the memory. very unfavorable;

[0009] 2. The distance between each memory cell is getting shorter and shorter, which reduces the width of the groove at the shallow trench isolation between floating gates

First, when the groove is filled, the density of the interlayer dielectric and the control gate located in the groove is reduced; further, there is a phenomenon of coupling interference between the floating gates of adjacent memory cells, specifically, due to There is an electric field effect between adjacent memory cells, and the threshold voltage (threshold voltage, VTH) of an unoperated memory cell will be affected by its adjacent memory cells that have been operated, and the floating gates of adjacent memory cells The interference of the unoperated memory cell causes the threshold voltage shift (VTH shift), which causes the reliability of the memory cell to decline

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