Novel two-dimensional coding reinforcing method and circuit arrangement for aerospace memory

Abstract

A two-dimensional coding reinforcing method for aerospace memories. Low-complexity multiple bit error detection and correction method is introduced into the reinforcing method, and the multiple bit error detection and correction method can carry out detection and correction on arbitrary multiple bit error. The reinforcing method comprises the following steps: 1, reading the word width of the memory, and logically converting a word with width N into a (k1, k2) two-dimensional matrix form; 2, determining the line number k1 and the column number k2 of the two-dimensional matrix; 3, adding a horizontal error detection code in each line, adding a vertical parity check code in each column; 4, when a word in the memory occurs multiple bit upsets, indicating the row and column the error respectively by the horizontal error detection code and the vertical parity check code; and when the interval of discontinuous multiple bit errors is less than L, giving a wrong signal by the horizontal error detection code; and 5, according to the amendment information bit, amending the information bits, and completing the amendment.

Description

technical field [0001] The invention relates to a two-dimensional code reinforcement method and a circuit device for an aerospace memory. Background technique [0002] With the reduction of IC process size and supply voltage, memory is more sensitive than ever to soft errors caused by space radiation environment and ground noise environment. The memory occupies more than 60% of the chip area of ​​the integrated circuit system, and most of the failures in the system are caused by the memory. Therefore, the research on memory hardening technology is one of the most important ways to improve the reliability of the integrated circuit system. Charged high-energy particles, protons and neutrons in the space environment, and alpha particles in the ground environment may cause single event upsets and multiple bit upsets to the memory, thereby affecting the correctness of stored data ] . When the IC process size is reduced below the deep submicron level (<0.18μm), the impact of ...

AI Technical Summary

Problems solved by technology

However, there are certain limitations and defects in the layout bit interleaving technology: the bit interleaving technology makes the word and column selection wiring of the memory longer, which has a negative impact on the area, data access time and power consumption, and when the number of interleaved bits increases, The above problems will be more obvious

When the radiant energy is further increased, they will not be able to correct more errors

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