Low-thickness and low-cost chip size package with cavity

Abstract

The invention discloses a low-thickness and low-cost chip size package with a cavity, and belongs to the field of packaging of semiconductors. The package structure comprises a cover plate, a wafer, a function region, bonding pads, bonding glue, silicon through holes, a redistribution circuit layer and a solder ball, wherein a cavity structure is formed in the front surface of the cover plate; the wafer comprises a wafer front surface and a wafer back surface; the function region and the bonding pads are distributed on the wafer front surface; the bonding pads are distributed on the periphery of the function region and are communicated with one another; the bonding glue is positioned between the cover plate and the wafer; the cover plate and the wafer are bonded together by the bonding glue; the bonding pads are exposed via the silicon through holes, so that the bonding pads are communicated with the a follow-up redistribution layer; the redistribution circuit layer is positioned on the wafer back surface and comprises a passivation layer, a metal layer and a solder layer; the bonding pads are communicated with the solder ball via the redistribution circuit layer; and the solder ball is positioned on the redistribution circuit layer of the wafer back surface. The thickness of the package is reduced, and the stress in the structure is also reduced. Moreover, the yield of a cutting process and the reliability of the package are improved.

Description

technical field [0001] The invention relates to a low-thickness and low-cost chip size package with a cavity, which belongs to the field of semiconductor packages. It can be preferably used in image sensors, MEMS devices or integrated chips, etc. Background technique [0002] Chip Scale Package (CSP) is a new generation of chip packaging technology, and its technical performance has been improved again. CSP packaging can make the ratio of chip area to package area exceed 1:1.14, which is quite close to the ideal situation of 1:1. The absolute size is only 32 square millimeters, which is about 1 / 3 of ordinary BGA, which is only equivalent to thin and small One-sixth the area of ​​a TSOP memory chip. Compared with ordinary ball grid array package (BGA), CSP package can increase the storage capacity by three times in the same space. The purpose of CSP is to use high-density chips (chips with more functions, better performance, and more complex chips) to replace previous chip...

AI Technical Summary

Problems solved by technology

Since the area to be cut contains a variety of materials with different hardness such as redistribution circuit layer, silicon, polymer, and cover plate 100, this poses a great challenge to the cutting process, and it is easy to generate fragments, slivers, etc.

On the other hand, during the subsequent service of the packaged product, since the metal layer 107 is in direct contact with the outside world around the package structure, once delamination occurs between the interfaces, it is easy to introduce moisture from the external environment into the package structure. , resulting in accelerated failure of the device

[0007] 3. When using TSV 105 technology, there are still many challenges in the preparation of TSVs with high aspect ratio due to the existing technology

First of all, its cost has always been high, and secondly, in the manufacturing process, such as: hole etching, electroplating filling and other process steps of TSV 105, there are complex processes and low product yields.

When the aspect ratio of the TSV 105 is higher, the challenge is more severe

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