TSV hole manufacturing technology
A manufacturing process and seed layer technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as high process requirements, many steps, and increased RDL manufacturing process
Inactive Publication Date: 2015-04-29
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Problems solved by technology
[0003] The existing TSV process has many steps and high process requirements. After the TSV is filled with electroplating, there is a layer of overburden. The removal of the overburden layer requires a CMP process. The cost of the CMP process is high. To achieve direct three-dimensional When interconnecting, it is necessary to further manufacture the RDL, so that the RDL is connected to the metal pad at the bottom of the TSV, which increases the RDL manufacturing process
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[0022] The present invention will be further described according to the accompanying drawings.
[0023] A kind of TSV hole manufacturing process, it comprises the following steps:
[0024] See figure 1 , (1), making TSV holes 2 on wafer silicon substrate 1; see figure 2 , (2), all the insulating layer 3 is made on the opening side of the TSV hole 2, and the insulating layer 3 can be a polymer or a material such as silicon oxide;
[0025] See image 3 , (3), coating a sacrificial layer material that can be patterned on the TSV hole, and patterning to form a hole and redistribution (RDL) layer pattern, the material of the sacrificial layer is photoresist; see Figure 4 , (4), forming a seed layer 5 on the polymer insulating layer 3 and photoresist 4 on the opening side of the TSV hole 1;
[0026] See Figure 5 , (5), performing electroplating filling on the seed layer 5, forming an electroplated metal layer 6;
[0027] See Figure 6 , (6), the first step is to remove the...
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The invention provides a TSV hole manufacturing technology. The technology steps are simple, the technological requirement is low, the CMP technology and the RDL manufacturing technology are omitted, and technology cost is well reduced. The TSV hole manufacturing technology comprises the following steps that 1, TSV holes re formed in a wafer silicon substrate; 2, insulating layers are formed on the open sides of the TSV holes respectively; 3, the TSV holes are coated with sacrificial layer materials which can be patterned, patterns of holes and wiring-again RDL layers are formed through patterning; 4, seed layers are formed on the insulating layers located on the open sides of the TSV holes and the sacrificial layer materials respectively; 5, electroplating and filling are conducted on the seed layers, and electroplating metal layers are formed; 6, optical resist on the wafer silicon substrate and the seed layers and the electroplating metal layers corresponding to the optical resist are eliminated, and RDL layers are formed.
Description
technical field [0001] The invention relates to the technical field of microelectronics manufacturing or processing semiconductor or solid device methods, in particular to a TSV hole manufacturing process. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption continue to increase. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional interconnection gradually becomes the limit to improve the performance of the semiconductor chip. bottleneck. The Through Silicon Via (TSV) process can realize direct three-dimensional in...
Claims
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IPC IPC(8): H01L21/768
CPCH01L21/76898
Inventor 靖向萌
Owner NAT CENT FOR ADVANCED PACKAGING