OTP (one-time programmable memory) device and manufacturing method thereof

Abstract

The invention discloses an OTP (one-time programmable memory) device which comprises a PMOS (p-channel metal oxide semiconductor) transistor and a PNPN thyristor, wherein the PNPN thyristor is positioned on the source region side of the gate structure of the PMOS transistor; a first P+ doped regions and a source region of the PNPN thyristor are shared, and a first N+ doped region is positioned between two P+ doped regions and in lateral contact with the P+ doped regions; the cathode, the anode and the control electrode of the PNPN thyristor are led out of an N well, the first P+ doped region and a second P+ doped region respectively, and a bit line is led out of the first N+ doped region; the state of the OTP device is determined through whether thermal breakdown between the first P+ doped region and the first N+ doped region is formed or not. The invention further discloses a manufacturing method for the OTP device. According to the OTP device and the manufacturing method, the device area can be reduced, so that the integration level of the device is increased and the compatibility between the device and a CMOS (complementary metal oxide semiconductor) process can be improved; programming current is relatively small, so that programming can be carried out by current pulses generated by circuits, without externally applied current pulses.

Description

technical field [0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a one-time programmable (one-time programmable memory, OTP) device; the present invention also relates to a manufacturing method of the OTP device. Background technique [0002] OTP device is a common non-volatile memory (NVM), which has more applications in embedded NVM with limited density and limited performance. Traditional electrically erasable programmable read-only memory (EEPROM), S0NOS, embedded flash memory (E-Flash) NVM is expensive. OTP devices and CMOS-compatible embedded NVM technology is a successful solution in the current industry, and has been widely used in applications such as analog technology trimming from the bit level to the kilobit level of data or code storage. . [0003] There are many types of structural designs of OTP memory cells. There are mainly two types of representative ones: [0004] Such as Figure 1A S...

AI Technical Summary

Problems solved by technology

Compared with the existing first OTP device, the existing second OTP device has a large reduction in the memory area; but because the floating gate is used as the electronic memory, the data storage capacity must have a certain limit for the thickness of the gate oxide film. As the requirements of NVM data storage, the theoretical value of the gate oxide film thickness is required to be above 60A, which is greater than the thickness of the gate oxide film used in the standard CMOS process. In this way, OTP is limited as an embedded part of the standard CMOS process. use

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