A kind of ldmos transistor structure and preparation method thereof

Abstract

The present invention provides an LDMOS transistor structure and a preparation method thereof, at least comprising a semiconductor substrate, a first high voltage well region, a second high voltage well region, a third high voltage well region, a first shallow trench isolation region, and a second shallow trench an isolation region, a third shallow trench isolation region, a source region, a drain region, a body lead region, a gate region and a contact hole, and the contact holes are respectively arranged in the source region, the drain region, the body lead region and the gate region Above, the contact holes arranged on the gate region are vertically distributed on one side of the gate polysilicon layer above the second shallow trench isolation region. In the present invention, the contact holes are rearranged and distributed on the gate polysilicon layer above the second shallow trench isolation region, so that the electric field distribution on the gate region is more uniform, and the intersection of the active region and the gate region will not be reached. Any negative impact, from the design to reduce the area occupied by the LDMOS device in the entire chip, in order to achieve the final customer chip size reduction.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an LDMOS transistor structure and a preparation method thereof. Background technique [0002] LDMOS (Laterally Diffused MOSFET, laterally diffused MOS transistor) is a power MOS transistor. Due to its ability to withstand high voltage (such as 24V) and high current density (such as 2A / mm) in the BCD (Bipolar-CMOS-DMOS) process 2 ), so LDMOS devices are usually used as switching tubes as the final output driver. The withstand voltage capability of the LDMOS device is proportional to the size of the lightly doped region and the distance of the level drop. The higher the design withstand voltage, the larger the required size. Therefore, the LDMOS device that can withstand high voltage and high current must occupy a large area. block chip area. [0003] Figure 1a It is a schematic structural diagram of an LDMOS transistor in the prior art, Figure 1b for Figure 1a...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an LDMOS transistor structure and its preparation method, which are used to solve the problem of large lead-out resistance of the gate region and uneven electric field distribution on the gate region in the prior art. The working environment of the LDMOS device is unstable, which leads to the problem of the breakdown of the LDMOS device and the excessive area occupied by the LDMOS device in the entire chip, which limits the vertical width of the gate on the active region, making the charge and discharge of the device work slowdown problem

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