Si-based low leakage current cantilever beam gate CMOS (complementary metal oxide semiconductor) transmission gate and preparation method thereof

Abstract

The invention relates to a Si-based low leakage current cantilever beam gate CMOS (complementary metal oxide semiconductor) transmission gate and a preparation method thereof. The transmission gate is composed of a cantilever beam gate NMOS (N-channel metal oxide semiconductor) transistor and a cantilever beam gate PMOS (P-channel metal oxide semiconductor) transistor. The MOS transistor of the transmission gate is prepared on a silicon substrate, and a grid electrode of the MOS transistor is suspended above a gate oxidation layer so as to form a cantilever beam structure. Electrode plates are designed below each cantilever beam gate. Pull-down voltage of the cantilever beam gate is designed to be equal to an absolute value of threshold voltage of the MOS transistor. When voltage between the cantilever beam gate and the electrode plates is less than the absolute value of the threshold voltage, the cantilever beam gate is suspended above the gate oxidation layer, and only when the voltage between the cantilever beam gate and the electrode plates reaches or is greater than the absolute value of the threshold voltage, the cantilever beam gate is pulled down to and attached to the gate oxidation layer. If the input end and the output end are different in level value at the time, the MOS transistor is conducted. The field intensity in the gate oxidation layer is low when the Si-based low leakage current cantilever beam gate CMOS transmission gate is in operation, so that the gate leakage current is reduced, and the power consumption is reduced effectively.

Description

technical field [0001] The invention provides a silicon-based low-leakage current cantilever beam gate CMOS transmission gate, which belongs to the technical field of micro-electromechanical systems. Background technique [0002] With the emergence of various modern mobile and portable devices, the heat dissipation performance and battery life of electronic devices are facing huge challenges. At the same time, with the development of integrated circuits, the integration of chips is getting higher and higher, the feature size of devices is shrinking, the number of integrated MOS tubes in chips is increasing sharply, and the clock frequency is getting higher and higher. A large number of MOS tubes work at a very high frequency, resulting in an increasing power consumption of the chip. This is contrary to the requirements of modern electronic equipment for low power consumption. Not only that, excessive power consumption will overheat the chip, which will not only reduce the ...

AI Technical Summary

Problems solved by technology

The power consumption of the chip has also become an important issue that chip designers must care about

Images