A Multicast Router Based on Packet Circuit Switching Technology and Its Working Mode

A switching technology and working method technology, applied in the field of on-chip network communication, can solve problems such as increased power consumption and area, waste of network bandwidth, and inability to provide parallel processing capabilities

Active Publication Date: 2018-01-19
HEFEI UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] (1) Poor scalability;
[0004] (2) The resource utilization rate is low and cannot provide good parallel processing capability;
[0005] (3) Significant increase in power consumption and area caused by global synchronization of a single clock
However, current research on "packet circuit" switching technology is limited to unicast communication functions
If the unicast communication function is used to realize that a requester node sends the same batch of data to multiple destination nodes, the data sent by the requester node to each destination node must go through the link establishment stage, data transmission stage, and link withdrawal stage, which seriously wastes network bandwidth and consumes more data transmission time

Method used

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  • A Multicast Router Based on Packet Circuit Switching Technology and Its Working Mode
  • A Multicast Router Based on Packet Circuit Switching Technology and Its Working Mode
  • A Multicast Router Based on Packet Circuit Switching Technology and Its Working Mode

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Embodiment Construction

[0084]In this embodiment, a multicast router based on "packet circuit" switching technology is applied to an on-chip network composed of several multicast routers, several resource nodes, and several interconnection channels. Each resource node Connected to a multicast router through an interconnection channel; any two adjacent multicast routers are adjacent to each other through an interconnection channel; a two-dimensional grid is formed by adjacent multicast routers; on any vertex of a two-dimensional grid The multicast router of the vertex is the starting coordinate point (1, 1); the two interconnected channels connected by the multicast router on the vertex are respectively the X axis and the Y axis, and the coordinate system OXY is established; and the positive direction of the X axis is the east direction, the negative direction of the X-axis is the west direction, the positive direction of the Y-axis is the north direction, and the negative direction of the Y-axis is th...

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Abstract

The invention discloses a multicast router based on "packet circuit" switching technology and its working mode, which is characterized in that it is applied to an on-chip network composed of several multicast routers, several resource nodes and several interconnection channels. A multicast router includes: an input state machine module, a priority encoder module, a decoder module, an address filter module, an arbitrator module, a crossbar module and an output state machine module; in a multicast data transmission transaction, a single requester node can at most At the same time, it supports sending the same batch of data to eight destination nodes at the same time; and the success rate of link establishment can be improved through the priority encoder module, and the destination node can avoid repeated routing through the address filtering module. The invention can make full use of the parallelism feature of the on-chip network, save the time spent on sending the same batch of data transactions from a single requester node to multiple destination nodes, and reduce the consumption of cache resources of multicast routers in the on-chip network.

Description

technical field [0001] The invention belongs to the technical field of on-chip network communication, in particular to the design of a multicast router based on "packet circuit" switching technology. Background technique [0002] With the continuous expansion of integrated circuit integration, the chip has gradually developed from a single function to a multi-functional system chip. Nowadays, a multifunctional system on chip (SoC, System on Chip) has been widely used. However, as the process feature size becomes smaller and smaller and the operating frequency rises rapidly, the shortcomings of the system-on-chip based on the bus architecture are gradually revealed. Mainly manifested in: [0003] (1) Poor scalability; [0004] (2) The resource utilization rate is low and cannot provide good parallel processing capability; [0005] (3) The power consumption and area caused by the global synchronization of a single clock greatly increase. [0006] In order to overcome the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/761H04L12/771H04L45/16H04L45/60
Inventor 宋宇鲲戴继祥张多利杜高明李世元
Owner HEFEI UNIV OF TECH
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