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N-type LDMOS device and technical method thereof

A process method, N-type technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of low on-resistance, reduce device breakdown voltage, etc., and achieve low on-resistance, on-current The effect of increasing and decreasing the surface electric field strength

Inactive Publication Date: 2015-12-09
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

It is usually necessary to add an additional N-type implant in the drift region of the device to make the device have a lower on-resistance, and this method will reduce the breakdown voltage of the device

Method used

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  • N-type LDMOS device and technical method thereof
  • N-type LDMOS device and technical method thereof
  • N-type LDMOS device and technical method thereof

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Embodiment Construction

[0032] The N-type LDMOS device described in the present invention is as Figure 10 As shown, there is an N-type buried layer 102 on a low-resistance substrate 101 with a resistivity of 0.007-0.013 Ω·cm. On the buried layer 102 is an N-type epitaxy 103, and there are P wells abutting against each other in the N-type epitaxy 103. 107 and drift zone 108;

[0033] The drift region 108 also has an N well 106 and an STI isolation structure 105;

[0034] The source region 112 of the LDMOS device is provided in the P well 107, and the drain region 112 of the LDMOS device is provided in the N well 106 of the drift region 108 (both heavily doped N-type regions, using the same reference numeral);

[0035] The P well 107 also has a heavily doped P-type region 113, leading out the P well 107; the P well 107 is used as a channel region of the LDMOS device;

[0036] The N-type epitaxy 103 has a gate oxide layer 109 and a polysilicon gate 110 on the surface of the LDMOS device, and the two ...

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Abstract

The invention discloses an N-type LDMOS device and a technical method thereof. According to the device, a low resistance substrate is provided with an N-type buried layer thereon. The N-type buried layer is provided with an N-type epitaxy thereon. The N-type epitaxy is provided with a P-well and a drift region therein. The drift region is also provided with an N-well and an STI structure therein. The P-well is also provided with a source region of the LDMOS device therein. The N-well of the drift region is provided with a drain region of the LDMOS device therein. The P-well is also provided with a heavily doped P-type region therein so as to draw forth the P-well. The surface of the N-type epitaxy is provided with a gate oxide layer and a polycrystalline silicon gate of the LDMOS device, and the two sides of the polycrystalline silicon gate are side walls. The bottom portion of the STI structure in the drift region is provided with heavily doped polycrystalline silicon. The P-type doped polycrystalline silicon layer is added to the bottom portion of the STI structure in the drift region, a P-type auxiliary exhaustion region is formed above the drift region, and a surface electric field intensity is lowered, which enable the LDMOS device to have a lower on-resistance and at the same time a higher breakdown voltage. The invention also discloses a technical method of the N-type LDMOS device.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to an N-type LDMOS device, and the invention also relates to a process method of the N-type LDMOS device. Background technique [0002] Due to its characteristics of high voltage resistance, high current drive capability and extremely low power consumption, it is currently widely used in power management circuits. In LDMOS (LaterallyDiffusedMetalOxideSemiconductor) devices, on-resistance is an important indicator. Such as figure 1 As shown, it is a schematic structural diagram of a traditional LDMOS device, its source region and drain region are heavily doped N-type regions 112, located in the P well 107, and the P well 107 also has a heavily doped P-type region 113 to connect the P-type well lead out, located in the N well 106. In the BCD (Bipolar-CMOS-DMOS) process, although DMOS and CMOS are integrated in the same chip, due to the requirements of high withstan...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/06
CPCH01L29/7816H01L29/0607H01L29/0611H01L29/66681
Inventor 石晶钱文生刘冬华胡君段文婷
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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