Semiconductor packaging member and manufacturing method thereof

Abstract

The invention provides a semiconductor packaging member and a manufacturing method thereof. The manufacturing method comprises the steps of: firstly, providing a bearing member with a semiconductor member, then forming a packaging layer with at least one opening on the bearing member, and enabling the packaging layer to cover the semiconductor member, wherein side surfaces of the openings are flat and smooth surfaces; and then forming a circuit layer, which is provided with conductors formed in the openings, on a second surface of the packaging layer, and then removing the bearing layer. According to the invention, the packaging layer and the openings are simultaneously formed, the wall surfaces of the openings are prevented to be too coarse, and the manufacturing time is greatly shortened.

Description

technical field [0001] The invention relates to a packaging process, in particular to a semiconductor package capable of avoiding the problem of laser drilling and its manufacturing method. Background technique [0002] With the evolution of semiconductor packaging technology, semiconductor devices (Semiconductordevice) have developed different packaging types, and in order to improve electrical functions and save packaging space, different three-dimensional packaging technologies have been developed, for example, fan-out package stacking (FanOutPackageonpackage, referred to as FOPoP), etc., to cooperate with the greatly increased number of input / output ports on various chips, and then integrate integrated circuits with different functions into a single package structure. The integration feature allows electronic components with different functions, such as memory, central processing unit, graphics processor, image application processor, etc., to achieve system integration t...

AI Technical Summary

Problems solved by technology

[0010] However, in the existing manufacturing method of the semiconductor package 1, since a plurality of openings 130 are formed by laser, the thermal effect of the laser will cause the wall surface of the opening 130 to be extremely rough (such as Figure 1C As shown in the rough surface 130a), so that when the conductive column 14 is produced by electroplating, the electroplating quality is not good, thus causing problems such as low yield rate and poor product reliability.

[0011] In addition, although the opening 130 can be formed by etching to avoid the occurrence of the rough surface 130a, if the opening 130 with a diameter of more than 100um is to be formed, the process time of the etching method is too long, and thus the cost will be greatly increased.

[0012] In addition, the thermal release layer 110 has flexibility, and its coefficient of thermal expansion (Coefficient of thermal expansion, CTE) and the lateral thrust generated by the flow of colloid when the encapsulation layer 13 is injected into the mold for encapsulation will affect the fixation of the semiconductor element 10 together. precision, that is, it is easy to cause the semiconductor element 10 to be offset, so that the semiconductor element 10 is not placed on the predetermined position of the thermalization release layer

Therefore, the alignment between the wiring redistribution layer 15 and the electrode pad 100 of the semiconductor element 10 will be offset, and when the size of the carrier 11 is larger, the positional tolerance between each of the semiconductor elements 10 will be increased accordingly. If the offset tolerance is too large, the wiring redistribution layer 15 cannot be connected to the electrode pad 100, that is, the electrical connection between the wiring redistribution layer 15 and the semiconductor element 10 will be greatly affected. , resulting in problems such as low yield rate and poor product reliability

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