Formation method of interconnect structure

Abstract

The invention provides a formation method for an interconnecting structure. The formation method comprises the steps of forming a dielectric layer on a semiconductor substrate; and then forming a silicon oxide masking layer on the dielectric layer for forming a hard mask, wherein the step of forming the silicon oxide masking layer is carried out by the steps of forming a tetraethyl orthosilicate layer on the dielectric layer firstly; then performing oxygen plasma processing on the tetraethyl orthosilicate layer to enable the oxygen plasma to react with the tetraethyl orthosilicate layer to form the silicon oxide masking layer. The carbon content in the silicon oxide layer formed by the technology is obviously reduced, so that the shortcoming that the consume rate of the silicon oxide masking layer is obviously less than that of the dielectric layer caused by the carbon atoms in a cleaning process for the through holes by a wet method after the through holes are formed by the subsequent dielectric layer is overcame, the flatness of the overall side wall of the openings formed in the hard mask and the through holes in the dielectric layer is effectively improved, therefore, the filling performance of the conductive materials subsequently filled to the through holes is improved, and the performance of a formed conductive plug is further improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming an interconnection structure. Background technique [0002] With the development of semiconductor technology, the integration level of semiconductor devices continues to increase, and the feature size (Critical Dimension, CD) of semiconductor devices becomes smaller and smaller. [0003] With the gradual reduction of the feature size of the semiconductor device, the RC delay (RC delay) problem of the interconnection structure has more and more influence on the semiconductor device. Reducing the K value of the dielectric layer material in the interconnection structure is an effective method to reduce the RC delay effect. In recent years, in the Back End of The Line (BEOL) of semiconductor devices, low K dielectric constant (Low K, LK) materials (K<3) and ultra-low K dielectric constant (Ultra Low K , ULK) material has gradually become the mainstrea...

AI Technical Summary

Problems solved by technology

[0007] However, in the actual operation process, it is found that the performance of the conductive plug formed by the existing technology is poor and cannot meet the development requirements of semiconductor technology. Therefore, how to improve the performance of the conductive plug is an urgent problem to be solved by those skilled in the art.

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