Wafer cutting method possessing test pattern

Abstract

The invention discloses a wafer cutting method possessing a test pattern. A copper interconnection test structure circuit and an on-line monitoring pattern are not put into a scribing groove area or the test structure circuit and the on-line monitoring pattern are not put into a scribing groove cutting area so that phenomena of chip collapse lack and stress hierarchy, which are generated because a problem that a thermal stress coefficient difference of copper, silicon oxide and a silicon nitride insulating layer is large because of scalability of the copper during a laser cutting process, are thoroughly avoided. Simultaneously, an extra chip with a high proportion can be acquired. In a technology after copper interconnection is completed, a silicon nitride film layer in the scribing groove area is removed so that only silicon oxide and silicon of a substrate exist in a profile map of the scribing groove area from top to bottom. Effective appearance of miniature cracks of the scribing groove area during a laser scanning process is effectively increased, cutting efficiency can be improved, and a yield of the chip after cutting and a packaging yield are increased.

Description

technical field [0001] The invention relates to the field of semiconductor preparation, in particular to a wafer cutting method with test patterns. Background technique [0002] During the chip manufacturing process, in order to test and monitor the parameters of the online manufacturing process, and to conduct the wafer electrical performance acceptance test on the chip after the process is completed, the relevant test structure is usually placed in the dicing groove area between the chip and the chip. Those skilled in the art call it the chip (or wafer) scribing groove area. [0003] At the same time, the advanced process chip copper interconnection process usually uses a low-K (low dielectric constant) insulating layer to improve the RCdelay (delay) effect, and uses a silicon nitride insulating layer under the copper interconnection metal layer to prevent copper diffusion. The test structure circuit and online monitoring pattern are placed in the scribing groove area. I...

AI Technical Summary

Problems solved by technology

But in cutting area 102 owing to be provided with test structure circuit and on-line monitoring pattern 101, and test structure circuit and on-line monitoring pattern 101 are generally copper test components (Cu-testkey), when cutting, very easily take place serious cracking and chip Due to the phenomenon of stress delamination, it also caused some damage to the chip, refer to Figure 3b shown

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