Wafer cutting method possessing test pattern

A cutting method and a technology for testing patterns, which are used in manufacturing tools, fine working devices, electrical components, etc., can solve the problems of chip damage, delamination, chip cracking stress, etc., to reduce the occupied area, improve cutting efficiency, improve The effect of the cut effect

Inactive Publication Date: 2016-02-17
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But in cutting area 102 owing to be provided with test structure circuit and on-line monitoring pattern 101, and test structure circuit and on-line monitoring pattern 101 are generally copper test c

Method used

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  • Wafer cutting method possessing test pattern
  • Wafer cutting method possessing test pattern
  • Wafer cutting method possessing test pattern

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0040] Example 1:

[0041] First, a wafer to be cut is provided, and 4a is a partial schematic view of the wafer to be cut, including a plurality of spaced chip regions 100 (shown as four chip regions), and each chip region 100 is provided with a scribe The dicing groove area 102 includes the dicing area 104 and the test assembly 101 . The test component 101 is a copper interconnected test structure circuit and an online monitoring pattern, and its main material is copper; and an insulating material layer is provided on the lower surface of the test component 101, preferably, the insulating material layer is a silicon nitride film , in order to avoid the downward diffusion of copper to cause damage to the device.

[0042] In this embodiment, the cutting area 104 and the test component 101 do not overlap, so that when cutting along the cutting area 104, no contact is formed with the copper interconnected test component 101, thereby avoiding the occurrence of copper The ductil...

Example Embodiment

[0043] Embodiment 2:

[0044] First, a wafer to be cut is provided, and 5a shows a partial schematic view of the wafer to be cut, including a plurality of spaced chip regions 100 , and a scribe groove region 102 is provided between adjacent chip regions 100 . A test component 101 is provided at the corner of each chip area 100 away from the dicing groove area 102 . The test component 101 is a copper interconnected test structure circuit and an online monitoring pattern, the material is copper, and is disposed on the lower surface of the test component 101 There is a layer of insulating material, preferably, the insulating material layer is a silicon nitride film, so as to avoid the downward diffusion of copper and damage to the device.

[0045] Since the test assembly 101 in the present invention is not arranged in the scribe groove area 102, the entire scribe groove area 102 can be directly cut as a cutting area, so the width of the scribe groove area 102 can be appropriately...

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Abstract

The invention discloses a wafer cutting method possessing a test pattern. A copper interconnection test structure circuit and an on-line monitoring pattern are not put into a scribing groove area or the test structure circuit and the on-line monitoring pattern are not put into a scribing groove cutting area so that phenomena of chip collapse lack and stress hierarchy, which are generated because a problem that a thermal stress coefficient difference of copper, silicon oxide and a silicon nitride insulating layer is large because of scalability of the copper during a laser cutting process, are thoroughly avoided. Simultaneously, an extra chip with a high proportion can be acquired. In a technology after copper interconnection is completed, a silicon nitride film layer in the scribing groove area is removed so that only silicon oxide and silicon of a substrate exist in a profile map of the scribing groove area from top to bottom. Effective appearance of miniature cracks of the scribing groove area during a laser scanning process is effectively increased, cutting efficiency can be improved, and a yield of the chip after cutting and a packaging yield are increased.

Description

technical field [0001] The invention relates to the field of semiconductor preparation, in particular to a wafer cutting method with test patterns. Background technique [0002] During the chip manufacturing process, in order to test and monitor the parameters of the online manufacturing process, and to conduct the wafer electrical performance acceptance test on the chip after the process is completed, the relevant test structure is usually placed in the dicing groove area between the chip and the chip. Those skilled in the art call it the chip (or wafer) scribing groove area. [0003] At the same time, the advanced process chip copper interconnection process usually uses a low-K (low dielectric constant) insulating layer to improve the RCdelay (delay) effect, and uses a silicon nitride insulating layer under the copper interconnection metal layer to prevent copper diffusion. The test structure circuit and online monitoring pattern are placed in the scribing groove area. I...

Claims

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Application Information

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IPC IPC(8): H01L21/78H01L23/544B28D5/00
Inventor 彭坤
Owner SEMICON MFG INT (SHANGHAI) CORP
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