A vdmos device and its manufacturing method
A production method, N-type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of inability to adjust the doping concentration, and achieve the effect of reducing resistance
Active Publication Date: 2019-05-07
FOUNDER MICROELECTRONICS INT
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Problems solved by technology
The existing process cannot adjust the doping concentration here alone
Method used
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Embodiment 1
[0085] In order to illustrate the technical solution of the present invention more clearly, Embodiment 1 is illustrated below in conjunction with the schematic structural diagram of the device formed in each step, as Figure 15 As shown, the above-mentioned production method may specifically include the following steps:
[0086] S10, sequentially forming an N-type epitaxial layer 2 and a first oxide layer 3 on an N-type substrate 1, such as image 3 shown;
[0087] Wherein, the growth temperature of the first oxide layer 3 is about 900-1100° C., and the thickness is about 0.02-0.01 um.
[0088] S11, forming a silicon nitride layer 4 on the first oxide layer 3, such as Figure 4 shown;
[0089] Wherein, the growth temperature of the silicon nitride layer 4 is about 600-900° C., and the thickness is about 0.02-0.01 um.
[0090] S12, forming a polysilicon layer 5 on the silicon nitride layer 4, such as Figure 5 shown;
[0091] Wherein, the growth temperature of the polysil...
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Abstract
The invention provides a manufacturing method of a VDMOS. The manufacturing method comprises the steps of: forming an N-type epitaxial layer, a first oxidation layer and a silicon nitride layer on an N-type substrate in sequence; forming a polycrystalline silicon layer on the silicon nitride layer, and etching the polycrystalline silicon layer to form grooves; forming a second oxidation layer on the surface of the polycrystalline silicon layer, carrying out P-type ion implantation on the N-type epitaxial layer to sequentially form a P- body region and a P+ region; carrying out N-type ion implantation on the N-type epitaxial layer to form an N+ source region; forming a dielectric layer in the grooves and on the polycrystalline silicon layer to obtain a first structure; and etching the first structure to form contact holes. The invention further provides a VDMOS device manufactured by adopting the manufacturing method. According to the VDMOS device and the manufacturing method thereof, resistance of a JFET region in the VDMOS is effectively reduced by implanting high-concentration N-type ions in the JFET region independently.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a VDMOS device and a manufacturing method thereof. Background technique [0002] Vertical double diffused metal - oxide semiconductor field effect transistor (VerticalDoubleDiffusionMetal.Oxide—SemiconductorFieldEfieetTransistor, VDMOS), both the advantages of bipolar transistors and ordinary MOS devices, whether it is switching applications or linear applications, VDMOS is an ideal power device, Mainly used in electrode speed regulation, inverter, uninterruptible power supply, electronic switch, hi-fi audio, automotive electrical appliances and electronic ballast, etc. [0003] The production process of conventional planar VDMOS is as follows: [0004] Step 1: growing a gate dielectric layer (gate oxide layer). Polysilicon is grown, and after photolithography and etching, a polysilicon gate is produced. [0005] The second step: performing implantation and...
Claims
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IPC IPC(8): H01L21/336H01L29/78H01L29/06H01L29/423
Inventor 马万里闻正锋
Owner FOUNDER MICROELECTRONICS INT