Plasma scribing chip packaging structure and manufacturing method

Abstract

The invention discloses a plasma scribing chip packaging structure and a manufacturing method. The structure comprises a chip, and the front surface of the chip is covered by one dielectric layer. The dielectric layer comprises at least one conductive pad, and at least one side wall of the chip is shaped like a rack which extends in an up / down direction. Moreover, each tooth slot of the rack is shaped like an arc. The side walls and back of the chip are completely coated by a passivation layer. In the structure, the passivation layer wraps the back and side walls of the chip, thereby avoiding the electric leakage, caused by the exposing of the base body of the chip, of the chip. The side walls of the chip are shaped like the rack, thereby facilitating the hanging and gluing, and increasing the binding force of the passivation layer with the side walls. The method employs a plasma dry method for etching, scribing and segmenting of a wafer, solves a problem of edge breakage when a blade mechanically cuts the chip, also solves a problem that the side walls of the chip are exposed because of a plasma separation method, and improves the feasibility of the technology.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a plasma dicing chip packaging structure and a manufacturing method. Background technique [0002] In the wafer-level packaging process of semiconductor chips, after the packaging is completed, they are cut and separated into individual chips, which has high packaging efficiency and low cost. Cutting is usually done mechanically with a blade, which is prone to edge chipping and takes a long time to cut, which affects production capacity. [0003] Plasma removes the barrier material at the dicing line of the wafer, mainly silicon, and the method of separating and forming a single chip is an ideal separation method from the perspective of chipping and production capacity. However, the silicon on the sidewall of the chip after plasma separation will be exposed, which will easily lead to leakage and lead to chip failure. Therefore, how to protect packaged chips in a...

AI Technical Summary

Problems solved by technology

[0004] At present, people in the field use the PECVD (Physical Vapor Deposition) process, which can better form a dielectric layer on the sidewall of the dicing line and the back of the chip, but the PECVD process uses plasma and high temperature conditions greater than 200 ° C, which is not suitable for temporary The reason for the bonding packaging solution is that plasma or high temperature conditions act on the temporary bonding adhesive to denature the temporary bonding adhesive, which will cause the chip to drop in other processes and affect the subsequent debonding process

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