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Transmission method of block sending communication network data

A communication network and transmission method technology, applied in the field of high-speed data communication, can solve problems such as low efficiency, control, and inability to real-time data flow, and achieve the effects of reducing coupling, ensuring transmission efficiency, and solving timing competition

Active Publication Date: 2019-03-19
10TH RES INST OF CETC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This method of avoiding congestion by shaking hands with the data receiving end is inefficient, and it is impossible to control the data flow in real time

Method used

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  • Transmission method of block sending communication network data
  • Transmission method of block sending communication network data
  • Transmission method of block sending communication network data

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Experimental program
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Embodiment Construction

[0024] In the embodiment described below, based on the PPC processor, DSP processor and FPGA with different characteristics of the high-speed switching RapidIO bus interconnection, a common communication component is designed by using the underlying hardware memory mapping communication mechanism of the RapidIO network , Complete communication resource management, data cache management, send and receive queue management, physical resource and logical resource association strategy to achieve high bandwidth requirements data transmission.

[0025] Refer to Figure 1-Figure 2 . The special processor DSP, general processor PPC and field programmable logic device FPGA in the field of digital signal processing are divided into high-speed bus layer, communication component layer and application program layer according to the same software architecture of heterogeneous systems. DSP and PPC's own peripheral RapidIO bus interface forms a high-speed bus layer. In the field programmable log...

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Abstract

The invention provides a transmission method for block communication network data sending and aims at providing a block data communication method enabling a several kind of different processor groups to work cooperatively and effectively. According to the technical scheme, the method comprises: a plurality of FPGAs, a DSP, and a PPC are connected mutually by bus interfaces to form a network; communication assemblies with completely identical codes are constructed on the bus interfaces of the DSP and the PPC and communication assemblies having the same software architecture as the DSP and the PPC are arranged on bus interfaces generated by IP cores of the FPGAs by using the programmable logic language; and block data channel descriptors of other communication nodes are configured dynamically and asynchronously by a network management communication node; high-speed bus internal memory mapping is divided into internal memory regions of the communication nodes and mapping into network addresses is realized, thereby forming a transmission mechanism of data block sending; and a sending communication node sends block data to a receiving communication node and the receiving communication node receive data based on a receiving descriptor, and data flow control is realized.

Description

Technical field [0001] The invention relates to a method for transmitting communication data for multiple types of processors in the field of high-speed data communication through RapidIO bus networking blocks. technical background [0002] With the increasing task of electronic systems, the system has higher and higher requirements for large-capacity data, highly complex algorithms and real-time computing speed. High-bandwidth, high-speed data transmission technology is one of the core technologies of high-speed data communication systems, wireless infrastructure devices, network access equipment, multi-service platforms, high-end routers, storage equipment, signal and image processing, military and aerospace applications, industrial In applications such as computing and scientific computing, different types of processors are usually used to complete high-speed data acquisition, signal processing and data processing. Due to the limited memory of the acceleration device in heter...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/801H04L12/825H04L12/863
CPCH04L47/12H04L47/25H04L47/50
Inventor 唐宇潘灵钟瑜
Owner 10TH RES INST OF CETC